13.
    发明专利
    未知

    公开(公告)号:DE60319366T2

    公开(公告)日:2009-04-02

    申请号:DE60319366

    申请日:2003-05-16

    Applicant: IBM

    Abstract: A Resource Reservation System includes a Token Generation Unit (TGU) which generates and circulates among nodes of a communications system a Slotted Token (SLT) message having sub-fields to carry identification number for each input port in a node and the resource available for each input port. On receiving the message the Resource Control Unit (RCU) in each node can write port identification number, available resource in appropriate sub-fields of the SLT message, and reserve resources in other nodes by adjusting information in the sub-field associated with the other nodes.

    14.
    发明专利
    未知

    公开(公告)号:BR0311224A

    公开(公告)日:2005-03-22

    申请号:BR0311224

    申请日:2003-05-16

    Applicant: IBM

    Abstract: A Resource Reservation System includes a Token Generation Unit (TGU) which generates and circulates among nodes of a communications system a Slotted Token (SLT) message having sub-fields to carry identification number for each input port in a node and the resource available for each input port. On receiving the message the Resource Control Unit (RCU) in each node can write port identification number, available resource in appropriate sub-fields of the SLT message, and reserve resources in other nodes by adjusting information in the sub-field associated with the other nodes.

    17.
    发明专利
    未知

    公开(公告)号:DE3484285D1

    公开(公告)日:1991-04-25

    申请号:DE3484285

    申请日:1984-03-30

    Applicant: IBM

    Abstract: A uniprocessor is formed on plural independently controlled chips (26, 28,30) each including a primary instruction driven controller (84) and a secondary error driven self-sequencing controller (102). Each instruction is supplied in parallel to each primary controller which generates an EXIT signal, as it completes execution, to a common external EXIT line (62). Hardware (116) monitors the local EXIT signal and the common EXIT line state and activates the secondary controller, when a mismatch is detected, to set an on-chip reset predominant error latch (124) driving a common external ERROR line (64), an ERROR-state on which also sets the latches and activates any inactive secondary controller to drive its chip to a first predetermined state and to reset its latch. When no ERROR signal remains, the secondary controllers cycle in synchronism through an ERROR routine, exiting to instruction control.

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