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    11.
    发明专利
    未知

    公开(公告)号：DE1260556B

    公开(公告)日：1968-02-08

    申请号：DEJ0018396

    申请日：1960-07-05

    Applicant: IBM

    Inventor： RUTZ RICHARD FREDERICK

    IPC: H01L21/00 ,  H01L27/00 ,  H01L29/00 ,  H03B7/08 ,  H03B7/14 ,  H03K3/315 ,  H03K19/10 ,  H03K19/162

    Abstract: 955,706. Tunnel-diode logical circuits; pulsing carrier frequencies. INTERNATIONAL BUSINESS MACHINES CORPORATION. June 29, 1960 [Oct. 14, 1959], No. 22769/60. Headings H3T and H4L. A logical circuit comprising an oscillator circuit as described in the parent Specification and consisting of a tunnel diode and another semi - conductor device so connected in a loop that the application of a suitable direct voltage across the tunnel diode initiates oscillations in the oscillator circuit, includes also a plurality of pulse input sources and an output circuit coupled to said oscillator circuit and is so biased in relation to the amplitudes of the input pulses that a predetermined combination of input pulses is required to bring the oscillator circuit to an oscillatory condition whereby an output signal is generated. In the circuit illustrated the oscillator circuit is composed of tunnel diode 3 and a resistance element 4 composed of two regions of heavily-doped N-type material connected in a closed loop by means of a conducting bar 5 and an earthed base 2. Power is supplied to the circuit from a source 16, which is shown as a cell but which may be replaced by a source of rectangular pulse signals, connected to the oscillatory loop through a resistor 15 whose resistance is high as compared to that of the element 4. Pulse input circuits comprise loops 8, 10 inductively coupled to the oscillator circuit; diodes 7, 9 are so poled as to prevent feed-back from the oscillator circuit to the input circuit. A further loop C serves as an output circuit and a further circuit coupled through a transformer 14 may serve as an additional input circuit, preferably for clockpulses. The inputs and/or outputs may alternatively be coupled capacitively to the circuit, Fig. 2 (not shown). The circuit is normally so biased by the source 16 that the tunnel diode 3 is operating on a positive-resistance portion of its characteristic; a suitable combination of input pulses will, however, convert it to a negative-resistance condition when it will oscillate and deliver an oscillatory output signal, which may be rectified, Fig. 5 (not shown), to provide a direct-current pulse output. Fig. 3 (not shown) illustrates biasing conditions suitable for making the circuit operate as an OR- circuit, an AND-circuit, an inverter circuit or a circuit having an " inhibit " operation. A plurality of the circuits may be arranged in parallel and cascaded with other circuits in which case the circuits should be energized from suitably phased pulse sources or delay circuits interposed between the stages, Fig. 4 (not shown). Two circuits may be cascaded as shown in Fig. 7, the connection between them being effected by a length of coaxial cable 49 serving as a delay line. Resistors 15 are provided by conductive coatings on insulating blocks 15a.

    16.
    发明专利
    未知

    公开(公告)号：DE1210488B

    公开(公告)日：1966-02-10

    申请号：DEJ0023881

    申请日：1963-06-15

    Applicant: IBM

    Inventor： RUTZ RICHARD FREDERICK

    IPC: H01L21/205 ,  H01L27/102

    Abstract: 1,000,382. Semi-conductor devices. INTERNATIONAL BUSINESS MACHINES CORPORATION. June 6, 1963 [June 18, 1962], No. 22663/63. Drawings to Specification. Heading H1K. A semi-conductor device comprises a high resistivity layer or body containing an aperture with heavily doped layers of opposite conductivity type material overlying opposite ends of the aperture, at least one of the layers extending into the aperture to form a PN tunnel junction with the other. A plurality of such devices may be made by forming conical or pyramidal pits in one face of a highly resistive (10 8 ohm. cm.) gallium arsenide wafer, vapour depositing heavily doped N-type germanium on the pitted face, lapping or etching the opposite face of the wafer to expose the N+ germanium at the bottoms of the pits and then depositing heavily doped germanium thereon to form an array of tunnel junctions with the exposed N + germanium. The array may, if desired, be split up into individual elements. To obtain better control over the tunnel junction area cylindrical apertures extending from the pit bottoms to the opposite wafer face are first formed from the opposite face by a photoresist masking and etching technique, by electron or laser beams, sandblasting or sparking. Then P + germanium is deposited on the pitted face to fill the apertures. After preferentially electrolytically etching back the P + material from the opposite face into the apertures N+ germanium is deposited on that face to form the junctions. In a modification of this method N germanium is deposited into the pits and where exposed through the apertures converted to N+ type by arsenic diffusion prior to deposition of P + germanium on the unpitted face. In each case one or both germanium layers may be replaced by gallium arsenide and the highly resistive wafer may alternatively be of zinc selenide. In one example of this, using P + gallium arsenide in the pits, the junctions are formed by alloying to the exposed P + material on the opposite face of the wafer. In another method the pits are replaced by parallel grooves and the heavily doped material deposited at the bases of the grooves exposed by cutting an intersecting set of parallel grooves in the opposite wafer face. Subsequently semi-conductor material is deposited in these grooves to form tunnel junctions at groove intersections. The junctions are interconnected either by continuing the deposition to fill the grooves with degenerate material or by providing metal layers over the deposited semiconductor. It is also suggested to design the tunnel diodes to have peak currents above the required level and to reduce the peak current by heat treatment. Finally devices may be formed by vapour depositing a layer of insulating gallium arsenide on one face of a degenerate P-type germanium wafer, forming small apertures in the layer and depositing degenerate N-type germanium over the layer to form junctions in the apertures. In this case the apertures are formed by etching through holes in a wax coating over the layer. Each hole is formed by pressing a metal point into the wax to substantially penetrate it, withdrawing it slightly, and then passing a high voltage discharge between it and the wafer to vaporize the wax under the point.

    17.
    发明专利
    未知

    公开(公告)号：DE1188676B

    公开(公告)日：1965-03-11

    申请号：DEJ0018083

    申请日：1960-05-05

    Applicant: IBM

    Inventor： RUTZ RICHARD FREDERICK

    IPC: H01L21/00 ,  H01L27/00 ,  H01L29/00 ,  H03B7/08 ,  H03B7/14 ,  H03K3/315 ,  H03K19/10 ,  H03K19/162

    Abstract: 955,706. Tunnel-diode logical circuits; pulsing carrier frequencies. INTERNATIONAL BUSINESS MACHINES CORPORATION. June 29, 1960 [Oct. 14, 1959], No. 22769/60. Headings H3T and H4L. A logical circuit comprising an oscillator circuit as described in the parent Specification and consisting of a tunnel diode and another semi - conductor device so connected in a loop that the application of a suitable direct voltage across the tunnel diode initiates oscillations in the oscillator circuit, includes also a plurality of pulse input sources and an output circuit coupled to said oscillator circuit and is so biased in relation to the amplitudes of the input pulses that a predetermined combination of input pulses is required to bring the oscillator circuit to an oscillatory condition whereby an output signal is generated. In the circuit illustrated the oscillator circuit is composed of tunnel diode 3 and a resistance element 4 composed of two regions of heavily-doped N-type material connected in a closed loop by means of a conducting bar 5 and an earthed base 2. Power is supplied to the circuit from a source 16, which is shown as a cell but which may be replaced by a source of rectangular pulse signals, connected to the oscillatory loop through a resistor 15 whose resistance is high as compared to that of the element 4. Pulse input circuits comprise loops 8, 10 inductively coupled to the oscillator circuit; diodes 7, 9 are so poled as to prevent feed-back from the oscillator circuit to the input circuit. A further loop C serves as an output circuit and a further circuit coupled through a transformer 14 may serve as an additional input circuit, preferably for clockpulses. The inputs and/or outputs may alternatively be coupled capacitively to the circuit, Fig. 2 (not shown). The circuit is normally so biased by the source 16 that the tunnel diode 3 is operating on a positive-resistance portion of its characteristic; a suitable combination of input pulses will, however, convert it to a negative-resistance condition when it will oscillate and deliver an oscillatory output signal, which may be rectified, Fig. 5 (not shown), to provide a direct-current pulse output. Fig. 3 (not shown) illustrates biasing conditions suitable for making the circuit operate as an OR- circuit, an AND-circuit, an inverter circuit or a circuit having an " inhibit " operation. A plurality of the circuits may be arranged in parallel and cascaded with other circuits in which case the circuits should be energized from suitably phased pulse sources or delay circuits interposed between the stages, Fig. 4 (not shown). Two circuits may be cascaded as shown in Fig. 7, the connection between them being effected by a length of coaxial cable 49 serving as a delay line. Resistors 15 are provided by conductive coatings on insulating blocks 15a.

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