公开(公告)号：DE69130583D1

公开(公告)日：1999-01-21

申请号：DE69130583

申请日：1991-02-11

Applicant: IBM

Inventor： OHBA NOBUYUKI ,  SHIMIZU SHIGENORI

IPC: G06F12/08 ,  G06F15/16 ,  G06F15/177

Abstract: Cache control system for a private cache in a multiprocessor data processing system comprising a plurality of processors each connected to a shared bus via similar private caches, the cache control system co-operating with similar cache control systems provided for other private caches in the data processing system, the cache control system comprising: a controller for monitoring signals on the shared bus and, when data shared between ones of the processors is modified in the cache, for performing one of two or more types of data consistency procedures for the shared data; and means for determining the relative likelihood of access to the shared data by the processor corresponding to the private cache and other processors in the system, the type of data consistency procedure performed by the controller being dependent on the results of the determination.

公开(公告)号：CA2062909C

公开(公告)日：1997-04-01

申请号：CA2062909

申请日：1992-03-12

Applicant: IBM

Inventor： MURATA HIROKI ,  SHIMIZU SHIGENORI

IPC: G06F12/08 ,  G06F15/167 ,  G06F15/16

Abstract: The bandwidth of the data transfer among a main memory and snoopy caches is improved by solving the bus neck in a multiprocessor system using a snoopy cache technique. Shared bus coupling is employed for an address/command bus requiring bus snoop whereas multiple data paths coupled by an interconnection network are used for the data bus not requiring bus snoop. The multiple data paths reflect the order of the snoopy operations on the order of data transfer such as to maintain data consistency among the caches.

公开(公告)号：BR9201347A

公开(公告)日：1992-12-01

申请号：BR9201347

申请日：1992-04-13

Applicant: IBM

Inventor： MURATA HIROKI ,  SHIMIZU SHIGENORI

IPC: G06F12/08 ,  G06F15/167 ,  G06F15/16

Abstract: The bandwidth of the data transfer among a main memory and snoopy caches is improved by solving the bus neck in a multiprocessor system using a snoopy cache technique. Shared bus coupling is employed for an address/ command bus 5 requiring bus snoop whereas multiple data paths coupled by an interconnection network 7 are used for the data bus not requiring bus snoop. The multiple data paths 7 reflect the order of the snoopy operations on the order of data transfer such as to maintain data consistency among the caches.

公开(公告)号：CA2062909A1

公开(公告)日：1992-10-23

申请号：CA2062909

申请日：1992-03-12

Applicant: IBM

Inventor： MURATA HIROKI ,  SHIMIZU SHIGENORI

IPC: G06F12/08 ,  G06F15/167 ,  G06F15/16

Abstract: The bandwidth of the data transfer among a main memory and snoopy caches is improved by solving the bus neck in a multiprocessor system using a snoopy cache technique. Shared bus coupling is employed for an address/ command bus 5 requiring bus snoop whereas multiple data paths coupled by an interconnection network 7 are used for the data bus not requiring bus snoop. The multiple data paths 7 reflect the order of the snoopy operations on the order of data transfer such as to maintain data consistency among the caches.