Distributed computing system
    1.
    发明专利
    Distributed computing system 有权
    分布式计算系统

    公开(公告)号:JP2005044204A

    公开(公告)日:2005-02-17

    申请号:JP2003278842

    申请日:2003-07-24

    CPC classification number: G06F21/6245 G06Q40/00 G06Q40/06

    Abstract: PROBLEM TO BE SOLVED: To prevent leakage of a parameter with high secrecy in a distributed computing system. SOLUTION: This distributed computing system for performing a plurality of partial computing operations is provided with a parameter storage means storing a parameter set constructed of a plurality of parameters, a conversion means converting a result of the partial computing operation and a linear parameter having a linearity into conversion parameters in each of a plurality of parameter sets, and a transmission means associating each of the converted parameter sets with parameter identification information about the parameter set and transmitting them for making a plurality of computing processors operate a plurality of partial computing operations. The distributed computing system is also provided with a conversion ratio storage means storing a conversion ratio of the parameter, a conversion ratio search means searching the conversion ratio matching the parameter identification information, and a reverse conversion output means generating results of the partial computing operation by multiplying the computing results by the reciprocal of the conversion ratio and outputting a pair of partial computing results. COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题:为了防止在分布式计算系统中高度保密的参数泄漏。 解决方案:用于执行多个部分计算操作的该分布式计算系统被提供有存储由多个参数构成的参数集的参数存储装置,转换部分计算操作的结果的转换装置和线性参数 对多个参数组中的每一个具有线性度转换参数;以及传输装置,将每个转换的参数集与参数集合的参数识别信息相关联,并发送它们以使多个计算处理器操作多个部分计算 操作。 分布式计算系统还设置有存储参数的转换比率的转换比率存储装置,搜索与参数识别信息匹配的转换比率的转换比搜索装置,以及产生部分计算操作的结果的逆转换输出装置, 将计算结果乘以转换比的倒数,并输出一对部分计算结果。 版权所有(C)2005,JPO&NCIPI

    SMALL-SIZED INFORMATION RECESSING EQUIPMENT

    公开(公告)号:JPH10240693A

    公开(公告)日:1998-09-11

    申请号:JP3901897

    申请日:1997-02-24

    Applicant: IBM

    Abstract: PROBLEM TO BE SOLVED: To provide an information processing equipment capable of realizing respectively suitable scrolling functions in the vertical and horizontal display modes. SOLUTION: At the time of a vertical display mode, when a rotary switch is operated clockwise, that is upwards along an equipment left side face, contents are scrolled upwards. On the contrary, when the rotary switch is operated counterclockwise, that is downwards along the equipment left side face, the contents are scrolled downwards. On the other hand, at the time of horizontally placing the equipment, the rotary switch is positioned at a lower left corner part. Then, at the time of a horizontal display mode, when the rotary switch is rotated clockwise, that is upwards along the equipment left side face (pertinent to the upper side face at the time of the vertical placement), the contents are scrolled upwards. On the contrary, when the rotary switch is dial- operated counterclockwise, that is downwards along the equipment left side face, the contents are scrolled downwards. The display contents are scrolled as they are by intuitively operating a single rotary switch in either of the vertical/horizontal display modes.

    DISK STORAGE DEVICE
    4.
    发明专利

    公开(公告)号:JPH086736A

    公开(公告)日:1996-01-12

    申请号:JP13468694

    申请日:1994-06-16

    Applicant: IBM JAPAN

    Abstract: PURPOSE:To write and read data fast through simple constitution. CONSTITUTION:This disk storage device is equipped with two data buses 100 and 200 for data transfer and an HDD 0 and an HDD 1 are connected fixedly to the data buses 100 and 200, respectively, and an MCU 32 outputs a specific signal to a DPC 10 according to a command from a host, and then multiplexers 20 and 22 connect the HDD 2 and HDD 3 to either of the data buses 100 and 200. Thus, the HDD 2 and HDD 3 are connected to one of the data buses 100 and 200 and data are written on and read out of HDDs 0-3.

    Asynchronous checkpoint acquisition in parallel computer calculation of iteration method and restoration from there
    5.
    发明专利
    Asynchronous checkpoint acquisition in parallel computer calculation of iteration method and restoration from there 有权
    并行计算机中异步检测点的迭代方法计算及其恢复

    公开(公告)号:JP2012178027A

    公开(公告)日:2012-09-13

    申请号:JP2011040262

    申请日:2011-02-25

    CPC classification number: G06F11/1438

    Abstract: PROBLEM TO BE SOLVED: To acquire a checkpoint when advancing computer calculation of an iteration method in parallel, and to efficiently utilize the acquired data upon restoration.SOLUTION: When acquiring the checkpoint in parallel calculation of repeating the iteration method such as time evolution calculation, calculation is not stopped independently in each node and the checkpoint is acquired in parallel with the calculation. Thus, the need of stopping the calculation during checkpoint acquisition time is eliminated, and the calculation and the checkpoint acquisition are simultaneously performed. When the calculation is not an I/O bottleneck, the checkpoint acquisition time is concealed and execution time is reduced. In the method, checkpoint data including values at different points of time during acquisition processing is acquired, and by limiting a use to convergence calculation of iteration method, coexistence of the values at the different points of time in the checkpoint data is allowed in the problem that a convergence destination is independent of an initial value.

    Abstract translation: 要解决的问题:在并行推进迭代方法的计算机计算时获取检查点,并且在恢复时有效地利用所获取的数据。

    解决方案:在重复迭代方法如时间演化计算的并行计算中获取检查点时,在每个节点中不独立地停止计算,并且与计算并行获取检查点。 因此,消除了在检查点采集时间期间停止计算的需要,同时执行计算和检查点采集。 当计算不是I / O瓶颈时,检查点获取时间被隐藏并且执行时间减少。 在该方法中,获取包括获取处理期间的不同时间点的检查点数据,并且通过限制对迭代方法的收敛计算的使用,在该问题中允许在检查点数据中的不同时间点处的值的共存 收敛目的地与初始值无关。 版权所有(C)2012,JPO&INPIT

    DATA STORAGE SYSTEM, DATA TRANSFER METHOD AND DATA RECONFIGURATION METHOD

    公开(公告)号:JPH09160723A

    公开(公告)日:1997-06-20

    申请号:JP31779795

    申请日:1995-12-06

    Applicant: IBM JAPAN

    Abstract: PROBLEM TO BE SOLVED: To prevent a data storage system from being complicated by transferring fast the data via data buses and also facilitating the control of the timing of the system. SOLUTION: The mutual synchronization of accesses is secured among storage means 13 to 17 which store the data. For this purpose, the data buses 11 and 12 are prepared to transfer the data together with an input/output means 21 which transfers the plural data series to the buses 11 and 12 with interleave, and a latch means 23 which is provided at plural stages and in series between the means 13 to 17 and the buses 11 and 12 and hold the data respectively.

    DATA STORAGE SYSTEM AND PARITY GENERATING METHOD THEREFOR

    公开(公告)号:JPH08202497A

    公开(公告)日:1996-08-09

    申请号:JP1043595

    申请日:1995-01-26

    Applicant: IBM JAPAN

    Abstract: PURPOSE: To facilitate transfer operation and restore data efficiently at a high speed in the case of fault occurrence by providing plural storage means, a data bus, and a selecting means having a function for parity arithmetic operation. CONSTITUTION: Two channels of 4-channel crossbar switches 11a and 11b having an exclusive OR operation function are connected to data buses DDO and DD1 as common buses. Other two channels of the crossbar switch 11a as the selecting means are connected to drives HDDO and HDD1. Other two channels of the crossbar switch 11b are connected to drives HDD2 and HDD3. Further, the crossbar switches 11a and 11b are controlled with an address signal and a control signal outputted from a data bus controller 13, and connections in optional combinations of drives and data buses are enabled. Thus, the selecting means itself is provided with the function for parity arithmetic operation.

    MULTIPROCESSOR SYSTEM AND DATA TRANSMITTER THEREFOR

    公开(公告)号:JPH04328653A

    公开(公告)日:1992-11-17

    申请号:JP11669391

    申请日:1991-04-22

    Applicant: IBM

    Abstract: PURPOSE: To improve the bandwidth of data transfer between a memory and a snoop cache by solving a bus bottleneck of a snoop cache type multiprocessor system. CONSTITUTION: A common bus connection is employed for an address/command bus 5 which requires bus snooping and a multiple data bus which is connected by an interconnection network 7 is used for a data bus which does not require bus snooping. The multiple data bus 7 has the order of snooping reflected on the order of data transfer enough to maintain the coincidence of data between caches.

    MULTIPROCESSOR SYSTEM AND DATA TRANSMISSION APPARATUS THEREOF

    公开(公告)号:CA2062909C

    公开(公告)日:1997-04-01

    申请号:CA2062909

    申请日:1992-03-12

    Applicant: IBM

    Abstract: The bandwidth of the data transfer among a main memory and snoopy caches is improved by solving the bus neck in a multiprocessor system using a snoopy cache technique. Shared bus coupling is employed for an address/command bus requiring bus snoop whereas multiple data paths coupled by an interconnection network are used for the data bus not requiring bus snoop. The multiple data paths reflect the order of the snoopy operations on the order of data transfer such as to maintain data consistency among the caches.

    10.
    发明专利
    未知

    公开(公告)号:BR9201347A

    公开(公告)日:1992-12-01

    申请号:BR9201347

    申请日:1992-04-13

    Applicant: IBM

    Abstract: The bandwidth of the data transfer among a main memory and snoopy caches is improved by solving the bus neck in a multiprocessor system using a snoopy cache technique. Shared bus coupling is employed for an address/ command bus 5 requiring bus snoop whereas multiple data paths coupled by an interconnection network 7 are used for the data bus not requiring bus snoop. The multiple data paths 7 reflect the order of the snoopy operations on the order of data transfer such as to maintain data consistency among the caches.

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