公开(公告)号：DE69213413D1

公开(公告)日：1996-10-10

申请号：DE69213413

申请日：1992-11-19

Applicant: IBM

Inventor： REILLY JOHN JOSEPH ,  VENTRONE SEBASTIAN THEODORE

IPC: G06F13/38 ,  G06F15/16 ,  G06F15/17 ,  G06F15/177

Abstract: A system for direct interprocessor communication in a multiprocessor data processing environment. The system utilizes conventional direct data transfer means and existing I/O port instruction capabilities available on most microprocessors. A destination processor requiring data from one of a source processor's internal registers generates a unique address which specifies the register containing the required data. The address is sent to the data transfer means, causing the direct transfer of data from the designated source processor internal register to the destination processor. Specific circuitry to accomplish this direct data transfer function is described.

公开(公告)号：DE3854212T2

公开(公告)日：1996-02-29

申请号：DE3854212

申请日：1988-05-20

Applicant: IBM

Inventor： LEVY JACK ROBERT ,  VENTRONE SEBASTIAN THEODORE

IPC: G06F12/02 ,  G06F9/355 ,  G06F9/34

Abstract: A signal generator provides circular addressing, i.e., performs basic modulo boundary indexing, which includes both positive and negative addressing, by adding an increment to a base register until a modulo boundary is reached without permitting the carry bit to propagate but instead resetting the address back to its lowest value. More particularly, the invention provides a signal generator which includes an adder having base address signals applied thereto from one of a plurality of registers and having an operand such as signals from an instruction data register (IDR) also applied thereto. Selected most significant bits from the output of the adder are applied to the input of a modulo mask function unit. Also applied to the input of the modulo mask function is a number of most significant bits of the base address signal. The carry bit from the adder is also applied to the input of the modulo mask function unit. The desired modulo is selected under the control of a decoder coupled to the modulo mask function unit. The output from the modulo mask function unit is applied to a common address register, along with the remaining least significant bits from the adder. In a preferred embodiment of the invention, the modulo mask function unit includes a plurality of passgates connected between the adder and the common address register and between the source of the most significant bits of the base address signals and the common address register.