公开(公告)号：EP1444563A4

公开(公告)日：2009-03-11

申请号：EP02780516

申请日：2002-10-22

Applicant: IBM

Inventor： SMITH JACK ROBERT ,  VENTRONE SEBASTIAN THEODORE

IPC: G06F1/04 ,  G06F1/32 ,  G06F15/78 ,  G06F1/26

CPC classification number: G06F1/3203

Abstract: In a first aspect, a method is provided for conserving power in a processing integrated circuit. This method includes the steps of calculating (401-408) power consumption for executing an instruction and data corresponding to the instruction; and executing (409, 410) the instruction if such execution does not exceed a predetermined power level. In a second aspect, a method is provided for conserving power in a processing integrated circuit employing a plurality of execution units. The method includes the steps of comparing (301, 302) a total power to be consumed by the processing integrated circuit to a power budget for the processing integrated circuit; and if the total power exceeds the power budget, freezing (304) execution of an instruction by one of the plurality of execution units so as to allow execution of the instruction to continue at a later time from where execution waSt frozen. Numerous other aspects are provided, as are systems and apparatus.

公开(公告)号：WO03036449A8

公开(公告)日：2004-08-26

申请号：PCT/US0233833

申请日：2002-10-22

Applicant: IBM

Inventor： SMITH JACK ROBERT ,  VENTRONE SEBASTIAN THEODORE

IPC: G06F1/04 ,  G06F1/32 ,  G06F15/78 ,  G06F1/26

CPC classification number: G06F1/3203

Abstract: In a first aspect, a method is provided for conserving power in a processing integrated circuit. This method includes the steps of calculating (401-408) power consumption for executing an instruction and data corresponding to the instruction; and executing (409, 410) the instruction if such execution does not exceed a predetermined power level. In a second aspect, a method is provided for conserving power in a processing integrated circuit employing a plurality of execution units. The method includes the steps of comparing (301, 302) a total power to be consumed by the processing integrated circuit to a power budget for the processing integrated circuit; and if the total power exceeds the power budget, freezing (304) execution of an instruction by one of the plurality of execution units so as to allow execution of the instruction to continue at a later time from where execution waSt frozen. Numerous other aspects are provided, as are systems and apparatus.

Abstract translation: 在第一方面，提供了一种用于在处理集成电路中节省功率的方法。 该方法包括计算（401-408）用于执行指令的功耗和对应于该指令的数据的步骤; 以及如果所述执行不超过预定功率电平则执行（409,410）所述指令。 在第二方面，提供一种用于在采用多个执行单元的处理集成电路中节省功率的方法。 该方法包括以下步骤：将处理集成电路要消耗的总功率（301,302）与处理集成电路的功率预算进行比较; 并且如果所述总功率超过所述功率预算，则通过所述多个执行单元中的一个来执行指令的冻结（304），从而允许执行所述指令在从执行waSt被冻结的较后时间继续执行。 还提供了许多其他方面，系统和装置也是如此。

公开(公告)号：DE3854212D1

公开(公告)日：1995-08-31

申请号：DE3854212

申请日：1988-05-20

Applicant: IBM

Inventor： LEVY JACK ROBERT ,  VENTRONE SEBASTIAN THEODORE

IPC: G06F12/02 ,  G06F9/355 ,  G06F9/34

Abstract: A signal generator provides circular addressing, i.e., performs basic modulo boundary indexing, which includes both positive and negative addressing, by adding an increment to a base register until a modulo boundary is reached without permitting the carry bit to propagate but instead resetting the address back to its lowest value. More particularly, the invention provides a signal generator which includes an adder having base address signals applied thereto from one of a plurality of registers and having an operand such as signals from an instruction data register (IDR) also applied thereto. Selected most significant bits from the output of the adder are applied to the input of a modulo mask function unit. Also applied to the input of the modulo mask function is a number of most significant bits of the base address signal. The carry bit from the adder is also applied to the input of the modulo mask function unit. The desired modulo is selected under the control of a decoder coupled to the modulo mask function unit. The output from the modulo mask function unit is applied to a common address register, along with the remaining least significant bits from the adder. In a preferred embodiment of the invention, the modulo mask function unit includes a plurality of passgates connected between the adder and the common address register and between the source of the most significant bits of the base address signals and the common address register.

公开(公告)号：MY117872A

公开(公告)日：2004-08-30

申请号：MYPI9705546

申请日：1997-11-19

Applicant: IBM

Inventor： MICHAIL MICHEL SALIB ,  PRICER WILBUR DAVID ,  VENTRONE SEBASTIAN THEODORE

IPC: G06F1/08 ,  G06F1/26 ,  G06F1/20 ,  G06F1/32

Abstract: A PROCESSOR(34) WHICH OPTIMIZES PERFORMANCE OPPORTUNISTICALLY BY USING A HIERARCHY OF VARIABLES COMPRISING VOLTAGE, CLOCKING AND THE OPERATIONS BEING PERFORMED BY THE PROCESSOR OR ITS SYSTEM. THE INVENTION ACCOMPLISHES PERFORMANCE OPTIMIZATION BY DEFINING VARIOUS STATES WITH THE GOAL THAT THE PROCESSOR STAYS IN AN OPTIMAL PERFORMANCE STATE OF ACCELERATED VOLTAGE AND CLOCK WHEN THE PROCESSOR EXECUTIONAL UNITS ARE OPERATING. THE STATES ARE SELECTED BY A LOGIC NETWORK(36) BASED ON INFORMATION THAT IS PROVIDED BY TEMPERATURE SENSORS AND A PERFORMANCE CONTROL(32). THE LOGIC NETWORK CAN BE ENVISIONED AS AN UP-DOWN COUNTER. THE COUNTER CAN BE ADVANCED UP OR DOWN THE STATE "LADDER" AS THE CONDITIONS WARRANT. (FIG. 2)

公开(公告)号：GB2523870A

公开(公告)日：2015-09-09

申请号：GB201419302

申请日：2014-10-30

Applicant: IBM

Inventor： VENTRONE SEBASTIAN THEODORE ,  GOODNOW KENNETH JOSEPH ,  OGILVIE CLARENCE ROSSER ,  WOODRUFF CHARLES ,  GRAF RICHARD STEPHEN

IPC: H01L25/065 ,  H01L21/768 ,  H01L23/48

Abstract: A heat conductive layer 308 is deposited on a first surface of a wafer of semiconductor chips 332. An insulating layer 312 is then deposited on top of the heat conducting layer. The heat conductive layer is etched to form vias that expose through-electrodes 305 on the first surface of each semiconductor chip. Conductive pads 316 are deposited on the through-electrodes on a second surface of each semiconductor chip. The semiconductor chips are stacked, wherein the conductive bumps of a second one of the semiconductor chips electrically contact the through-electrodes of a first one of the semiconductor chips through the vias of the first semiconductor chip and the conductive bumps of a third one of the semiconductor chips electrically contact the through-electrodes of the second semiconductor chip through the vias of the second semiconductor chip. The holes in the thermally conductive layer and the insulating layer may be formed by etching. The through electrodes may be copper pillars and an underfill may be applied between the bottom semiconductor chip and a substrate.

公开(公告)号：GB2320994B

公开(公告)日：2001-07-11

申请号：GB9726216

申请日：1997-12-12

Applicant: IBM

Inventor： GOODNOW KENNETH JOSEPH ,  MICHAIL MICHEL SALIB ,  PRICER WILBUR DAVID ,  VENTRONE SEBASTIAN THEODORE

IPC: H04L1/24 ,  H04L25/34 ,  H04L25/49

Abstract: A calibrated multi-voltage level system is disclosed having a network of devices, including a first and a second device. The first device comprises a processor for generating data, an encoding unit for encoding the data into a first data signal having multiple voltage levels, and a transmitting unit for transmitting the encoded data signal to the second device. The first device also comprises a calibration unit for sending a first calibration signal to the second device, and for storing a second calibration signal from the second device; and an adaptation unit for correcting the second data signal from the second device with the stored second calibration signal.

公开(公告)号：DE69213413T2

公开(公告)日：1997-03-13

申请号：DE69213413

申请日：1992-11-19

Applicant: IBM

Inventor： REILLY JOHN JOSEPH ,  VENTRONE SEBASTIAN THEODORE

IPC: G06F13/38 ,  G06F15/16 ,  G06F15/17 ,  G06F15/177

Abstract: A system for direct interprocessor communication in a multiprocessor data processing environment. The system utilizes conventional direct data transfer means and existing I/O port instruction capabilities available on most microprocessors. A destination processor requiring data from one of a source processor's internal registers generates a unique address which specifies the register containing the required data. The address is sent to the data transfer means, causing the direct transfer of data from the designated source processor internal register to the destination processor. Specific circuitry to accomplish this direct data transfer function is described.

公开(公告)号：MY133334A

公开(公告)日：2007-11-30

申请号：MYPI0304490

申请日：1997-11-19

Applicant: IBM

Inventor： MICHAIL MICHEL SALIB ,  PRICER WILBUR DAVID ,  VENTRONE SEBASTIAN THEODORE

IPC: G06F1/08 ,  G06F1/26 ,  G06F1/20 ,  G06F1/32

Abstract: A PROCESSOR (34) WHICH OPTIMIZES PERFORMANCE OPPORTUNISTICALLY BY USING A HIERARCHY OF VARIABLES COMPRISING VOLTAGE, CLOCKING AND THE OPERATIONS BEING PERFORMED BY THE PROCESSOR OR ITS SYSTEM.THE INVENTION ACCOMPLISHES PERFORMANCE OPTIMIZATION BY DEFINING VARIOUS STATES WITH THE GOAL THAT THE PROCESSOR STAYS IN AN OPTIMAL PERFORMANCE STATE OF ACCELERATED VOLTAGE AND CLOCK WHEN THE PROCESSOR EXECUTIONAL UNITS ARE OPERATING.THE STATES ARE SELECTED BY A LOGIC NETWORK (36) BASED ON INFORMATION THAT IS PROVIDED BY TEMPERATURE SENSORS AND A PERFORMANCE CONTROL (32). THE LOGIC NETWORK CAN BE ENVISIONED AS AN UP-DOWN COUNTER.THE COUNTER CAN BE ADVANCED UP OR DOWN THE STATE "LADDER" AS THE CONDITIONS WARRANT.(FIG 2)

公开(公告)号：SG66414A1

公开(公告)日：1999-07-20

申请号：SG1997004113

申请日：1997-11-21

Applicant: IBM

Inventor： MICHAIL MICHEL SALIB ,  PRICER WILBUR DAVID ,  VENTRONE SEBASTIAN THEODORE

IPC: G06F1/08 ,  G06F1/20 ,  G06F1/32

Abstract: A processor which optimizes performance opportunistically by using a hierarchy of variables comprising voltage, clocking and the operations being performed by the processor or its system. The invention accomplishes performance optimization by defining various states with the goal that the processor stays in an optimal performance state of accelerated voltage and clock when the processor executional units are operating. The states are selected by a logic network based on information that is provided by temperature sensors and a performance control. The logic network can be envisioned as an UP-DOWN counter. The counter can be advanced UP or DOWN the state "ladder" as the conditions warrant.

公开(公告)号：GB2320994A

公开(公告)日：1998-07-08

申请号：GB9726216

申请日：1997-12-12

Applicant: IBM

Inventor： GOODNOW KENNETH JOSEPH ,  MICHAIL MICHEL SALIB ,  PRICER WILBUR DAVID ,  VENTRONE SEBASTIAN THEODORE

IPC: H04L1/24 ,  H04L25/34 ,  H04L25/49

Abstract: The invention relates to the use of calibration signals to correct multi-voltage level data signals. A multi-level data signal and a calibration signal representing the maximum possible amplitude of the data signal are sent from a first device 15 to a second device 30 in a network 10. The second device stores the calibration signal in unit 18, compares its amplitude to that of the data signal and corrects the data signal accordingly. Similarly, the calibration unit of the first device stores calibration signals corresponding to the other devices connected to the network and uses the appropriate calibration signal to correct signals received from these devices. Initially, the first device may inquire whether multi-level communication with a second device is possible and if not, revert to binary data signals. In this way, the system is able to automatically handle the transfer of signals to devices which are not multi-level compatible.