公开(公告)号：JP2009147137A

公开(公告)日：2009-07-02

申请号：JP2007323331

申请日：2007-12-14

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： WATABE TADAYOSHI ,  USUI TAKAMASA

IPC: H01L21/3205 ,  H01L21/768 ,  H01L23/52

CPC classification number: H01L21/76843 ,  H01L21/76831 ,  H01L21/76846 ,  H01L21/76864 ,  H01L21/76867 ,  H01L21/76873 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device that prevents erosion of interconnects and vias while the interconnects and vias are well embedded, thus being excellent in reliability, and to provide a method of fabricating the same. SOLUTION: The method of fabricating the semiconductor device includes the steps of forming an insulating film onto a semiconductor substrate, forming a recess in the insulating film, forming a precursor film that includes a predetermined metal element on a surface of the insulating film where the recess is formed, reacting the precursor film with the insulating film through heat treatment to form an insulating self-forming barrier film having a chemical compound containing as main constituent elements of the predetermined metal element and insulating film at the boundary phase, removing the unreacted precursor film after the insulating self-forming barrier film is formed, forming a conductive film, made at least of one of Ru and Co, onto the insulating self-forming barrier film from which the unreacted precursor film has been removed, depositing a wiring material film onto the conductive film, and planarizing the wiring material film to form a wiring structure. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供一种在互连和通孔嵌入良好的同时防止互连和通孔的侵蚀的半导体器件，因此具有优异的可靠性，并提供其制造方法。 解决方案：制造半导体器件的方法包括以下步骤：在半导体衬底上形成绝缘膜，在绝缘膜中形成凹陷，在绝缘膜的表面上形成包含预定金属元素的前体膜 在形成凹部的情况下，通过热处理使前体膜与绝缘膜反应，形成绝缘自形成阻挡膜，其具有含有作为预定金属元素和绝缘膜的边界相的主要构成元素的化合物，除去 形成绝缘自成膜阻挡膜之后的未反应的前体膜，形成至少形成Ru和Co中的一种的导电膜到已除去未反应的前体膜的绝缘自形成阻挡膜上，沉积布线 在导电膜上形成膜，并平面化布线材料膜以形成布线结构。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2009135139A

公开(公告)日：2009-06-18

申请号：JP2007307745

申请日：2007-11-28

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： USUI TAKAMASA ,  WATABE TADAYOSHI

IPC: H01L21/768 ,  H01L21/3205 ,  H01L23/52 ,  H01L23/522

CPC classification number: H01L21/7682 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76864 ,  H01L21/76867 ,  H01L21/76873 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device that prevents oxidization of a barrier film in a wiring layer as well as leak of Cu from wiring, and to provide a method of manufacturing the same. SOLUTION: The semiconductor device includes: a semiconductor substrate (1); a first insulating film (3) which is formed on the semiconductor substrate and contains Cu; an interconnection (5) which is formed in a trench formed in the first insulating film; a barrier film (4) which is formed between the interconnection and first insulating film; a second insulating film (6) which is formed on the upper surface of the first interconnection, and is formed to a depth not deeper than that of the thickness of the interconnection in a hollow portion (321) between the side surface of the barrier film and the first insulating film. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供一种半导体器件，其防止布线层中的阻挡膜的氧化以及Cu从布线泄漏，并提供其制造方法。 解决方案：半导体器件包括：半导体衬底（1）; 形成在半导体衬底上并含有Cu的第一绝缘膜（3） 形成在形成在第一绝缘膜中的沟槽中的互连（5）; 形成在所述互连和所述第一绝缘膜之间的阻挡膜（4） 第二绝缘膜（6），其形成在第一互连件的上表面上，并且形成为在阻挡膜的侧表面之间的中空部分（321）中的深度不比互连的厚度深的深度 和第一绝缘膜。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2008147300A

公开(公告)日：2008-06-26

申请号：JP2006330851

申请日：2006-12-07

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： USUI TAKAMASA

IPC: H01L21/822 ,  H01L21/318 ,  H01L21/768 ,  H01L27/04

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device having an MIM capacitor with high capacity.
SOLUTION: The semiconductor device internally comprises the MIM capacitor composed of: a first capacitor electrode 103, a capacitor insulating film 104 formed on the surface of the first capacitor electrode 103 and including an insulating nitrogen-containing copper silicide film 104a thin and excellent in film quality; and a second capacitor electrode 108 formed on the capacitor insulating film 104. Thus, the capacity of the MIM capacitor is increased in the semiconductor device.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种具有高容量的MIM电容器的半导体器件。 解决方案：半导体器件内部包括MIM电容器，其包括：第一电容器电极103，形成在第一电容器电极103的表面上的电容器绝缘膜104，并且包括绝缘的含氮硅化铜膜104a，薄膜和 电影质量优异; 以及形成在电容绝缘膜104上的第二电容器电极108.因此，在半导体器件中，MIM电容器的容量增加。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2011249794A

公开(公告)日：2011-12-08

申请号：JP2011108285

申请日：2011-05-13

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： TSUMURA KAZUMICHI ,  USUI TAKAMASA

IPC: H01L23/522 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52

CPC classification number: H01L23/53238 ,  H01L21/76832 ,  H01L21/76834 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device in which it is possible to increase adhesive force between interconnection wiring and an overlying cap layer, and a method for manufacturing the same.SOLUTION: A method for manufacturing a semiconductor device comprises: forming metal interconnection wiring 310 including a natural oxide film thereon in a dielectric layer 305 on a semiconductor substrate 101; forming a first cap layer 405 covering at least partly the dielectric layer and the metal interconnection wiring, the first cap layer including a manganese atom or ion; and forming a second cap layer 410 of an insulating body on the first cap layer 405. The natural oxide film reacts with the first cap layer to form a manganese oxide between the first cap layer and the metal interconnection wiring.

Abstract translation: 要解决的问题：提供一种可以增加互连配线和上覆盖层之间的粘合力的半导体器件及其制造方法。 解决方案：一种用于制造半导体器件的方法包括：在半导体衬底101上的电介质层305中形成包括其上的自然氧化膜的金属互连布线310; 形成覆盖至少部分介电层和金属互连布线的第一盖层405，第一盖层包括锰原子或离子; 以及在第一盖层405上形成绝缘体的第二盖层410.自然氧化膜与第一盖层反应以在第一盖层和金属互连布线之间形成氧化锰。 版权所有（C）2012，JPO＆INPIT

公开(公告)号：JP2009272563A

公开(公告)日：2009-11-19

申请号：JP2008123903

申请日：2008-05-09

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： WATABE TADAYOSHI ,  USUI TAKAMASA ,  HAYASHI HIROMI

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L21/7682 ,  H01L21/76807 ,  H01L21/76828 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76873 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To improve reliability of wiring by preventing wiring metal from corroding due to water in an insulating film. SOLUTION: A semiconductor device having embedded wiring includes inter-wiring insulating films 111 and 112 having a groove 113 for wiring partially formed, a metal wiring layer 115 buried in the groove 113 for wiring of the inter-wiring insulating films 111 and 112 and forming a gap with a sidewall surface of the groove 113 for wiring, and a waterproof barrier layer 118 formed so as to cover a sidewall surface and an upper surface of the wiring layer 115. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：通过防止布线金属由于绝缘膜中的水而腐蚀而提高布线的可靠性。 解决方案：具有嵌入式布线的半导体器件包括具有用于部分形成的布线的槽113的布线间绝缘膜111和112，埋在用于布线布线绝缘膜111和布线布线的槽113中的金属布线层115 并且与用于布线的槽113的侧壁表面形成间隙，以及形成为覆盖布线层115的侧壁表面和上表面的防水阻挡层118.（C）2010， JPO和INPIT

公开(公告)号：JP2008258431A

公开(公告)日：2008-10-23

申请号：JP2007099533

申请日：2007-04-05

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： HAYASHI HIROMI ,  WATABE TADAYOSHI ,  USUI TAKAMASA

IPC: H01L21/768 ,  H01L21/318 ,  H01L23/522

CPC classification number: H01L21/76829 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76886 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device with an insulating film for suppressing the movement of moisture from an inter-wiring insulating film to an inter-via insulating film and reducing influence on an inter-wiring effective dielectric constant, and its manufacturing method. SOLUTION: The semiconductor device 1 by the embodiment of this invention comprises: a semiconductor substrate provided with a semiconductor element on a surface; wiring 2b formed on the semiconductor substrate; the inter-wiring insulating film 4b formed on the same layer as the wiring 2b; a first via 7a connected to the lower surface of the wiring 2b; a first inter-via insulating film 8a formed on the same layer as the first via 7a; a second via 7b connected to the upper surface of the wiring 2b; a second inter-via insulating film 8b formed on the same layer as the second via 7b; and a CuSiN film 9 formed at least either between the inter-wiring insulating film 4b and the first inter-via insulating film 8a or between the inter-wiring insulating film 4b and the second inter-via insulating film 8b. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 解决的问题：为了提供具有绝缘膜的半导体器件，用于抑制水分从布线间绝缘膜到通孔间绝缘膜的移动，并降低对布线间有效介电常数的影响，以及 其制造方法。 解决方案：通过本发明的实施例的半导体器件1包括：在表面上设置有半导体元件的半导体衬底; 形成在半导体基板上的布线2b; 形成在与布线2b相同的层上的布线间绝缘膜4b; 连接到布线2b的下表面的第一通孔7a; 形成在与第一通孔7a相同的层上的第一通孔间绝缘膜8a; 连接到布线2b的上表面的第二通孔7b; 形成在与第二通孔7b相同的层上的第二通孔间绝缘膜8b; 以及形成在布线间绝缘膜4b和第一通孔间绝缘膜8a之间或布线间绝缘膜4b和第二通孔间绝缘膜8b之间的至少任一个的CuSiN膜9。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2008153472A

公开(公告)日：2008-07-03

申请号：JP2006340506

申请日：2006-12-18

Applicant: Toshiba Corp ,  Toshiba Microelectronics Corp ,  東芝マイクロエレクトロニクス株式会社 ,  株式会社東芝

Inventor： USUI TAKAMASA ,  WATABE TADAYOSHI ,  NASU ISATO

IPC: H01L21/3205 ,  H01L21/768 ,  H01L23/52

CPC classification number: H01L21/76831 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76864 ,  H01L21/76873 ,  H01L21/76883 ,  H01L21/76888

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device having a low wiring resistance by decreasing the density of an impurity metal residing in a Cu wiring having a self-forming barrier film.
SOLUTION: A concave portion is formed on an Si-containing insulating film on a semiconductor substrate, and a precursor film made of CuMn is formed on the surface of the insulating film. A Cu film is deposited on the precursor film, and is thermally processed in an oxidized atmosphere to cause the precursor film to react with the insulating film to form a self-forming barrier film made of MnSiO on its boundary surface. Non-reacting Mn is allowed to diffuse and move in a wiring forming film, and to react with oxygen in the atmosphere on the surface of the wiring forming film, and precipitated as an MnO film. The MnO film is removed, Cu is further deposited on the Cu film and the wiring forming film is additionally deposited. The Cu film is planarized by a CMP method until the insulating film out of the concave portion is exposed, and a Cu wiring structure having a low Mn density is formed.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 解决的问题：提供通过降低驻留在具有自形成阻挡膜的Cu布线中的杂质金属的密度来制造具有低布线电阻的半导体器件的方法。 解决方案：在半导体衬底上的含Si绝缘膜上形成凹部，在绝缘膜的表面上形成由CuMn构成的前体膜。 在前体膜上沉积Cu膜，在氧化气氛中进行热处理，使前体膜与绝缘膜反应，在其界面形成由MnSiO构成的自形成阻挡膜。 使不反应的Mn扩散并在布线形成膜中移动，并与布线形成膜的表面上的大气中的氧反应，并且作为MnO膜沉淀。 除去MnO膜，再在Cu膜上沉积Cu，另外沉积布线形成膜。 通过CMP法将Cu膜平坦化，直到露出凹部以外的绝缘膜，形成Mn密度低的Cu配线结构体。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007305667A

公开(公告)日：2007-11-22

申请号：JP2006130339

申请日：2006-05-09

Applicant: Toshiba Corp ,  Toshiba Microelectronics Corp ,  東芝マイクロエレクトロニクス株式会社 ,  株式会社東芝

Inventor： NASU ISATO ,  USUI TAKAMASA

IPC: H01L21/60

CPC classification number: H01L24/48 ,  H01L23/3192 ,  H01L23/48 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/45 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05647 ,  H01L2224/05657 ,  H01L2224/11464 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48464 ,  H01L2224/48647 ,  H01L2224/48747 ,  H01L2224/48757 ,  H01L2224/48847 ,  H01L2224/48857 ,  H01L2224/8112 ,  H01L2224/81801 ,  H01L2224/83907 ,  H01L2224/85447 ,  H01L2224/8547 ,  H01L2224/85909 ,  H01L2224/9201 ,  H01L2224/9202 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/04953 ,  H01L2924/10253 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/48657 ,  H01L2924/00015 ,  H01L2224/45015 ,  H01L2924/207

Abstract: PROBLEM TO BE SOLVED: To reduce manufacturing time and manufacturing cost, and to suppress a drop of yield and reliability in a semiconductor device wherein a semiconductor chip and a lamination body are connected. SOLUTION: The semiconductor device is provided with a semiconductor chip 10 having a first pad 13, a lamination body 20 having a second pad 23 facing the first pad 13, and high melting-point metallic layers 15 and 25 which are directly in contact with the first and second pads 13 and 23, respectively, and are formed by the electroless plating method. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：为了减少制造时间和制造成本，并且抑制半导体芯片和层压体连接的半导体器件的产率和可靠性的下降。 解决方案：半导体器件设置有具有第一焊盘13的半导体芯片10，具有面向第一焊盘13的第二焊盘23的层叠体20和直接位于第一焊盘13中的高熔点金属层15和25 分别与第一和第二焊盘13和23接触，并通过无电镀方法形成。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2006140326A

公开(公告)日：2006-06-01

申请号：JP2004328847

申请日：2004-11-12

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： USUI TAKAMASA ,  SHIBATA HIDEKI ,  MUROFUSHI TADASHI ,  JINBO MASAKAZU ,  HIRAYAMA HIROSHI

IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/822 ,  H01L27/04

CPC classification number: H01L23/528 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device which can reduce the concentration of stress on a boundary between wiring and a low-dielectric insulated film, even if a low-dielectric insulated film is used as an interlayer insulated film for multilayer wiring, can suppress the peeling of the insulated film, and is provided with a wiring structure with improved heat dissipation performance. SOLUTION: The semiconductor device is provided with an insulated film ILD formed on the upper side of a semiconductor substrate, wiring M formed in the insulated film, and a mesh-like dummy structure ND which is formed apart from the wiring in the low dielectric insulated film. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：即使使用低介电绝缘膜作为多层的层间绝缘膜，可以提供能够降低布线与低介电绝缘膜之间的边界上的应力集中的半导体装置 布线可以抑制绝缘膜的剥离，并且设置有具有改善的散热性能的布线结构。 解决方案：半导体器件设置有形成在半导体衬底的上侧的绝缘膜ILD，以及形成在绝缘膜中的布线M以及网状假虚构结构ND，其与 低介电绝缘膜。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2005311123A

公开(公告)日：2005-11-04

申请号：JP2004126980

申请日：2004-04-22

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： TSUMURA KAZUMICHI ,  USUI TAKAMASA

IPC: H01L21/3205 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76849 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device including multilayer metalization construction by which an increase in line capacity is suppressed, and a problem of deterioration of leak characteristics between interconnections is avoided; and to provide its manufacturing method. SOLUTION: The semiconductor device comprises interconnections 117, 127, 137, conductive films 118, 128, 138 which prevent diffusion of wiring materials formed on the surface of an upper side of the interconnections, and insulating films of a lower dielectric constant, 111, 121, 131, 141 which are laminated to form at least two layers. Boundary surfaces include the insulating films positioned at side faces of the interconnections. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种包括多层金属化结构的半导体器件，其中线路容量的增加被抑制，并且避免了互连之间的泄漏特性劣化的问题; 并提供其制造方法。 解决方案：半导体器件包括互连117,127,137，防止形成在互连的上侧表面上的布线材料扩散的导电膜118,128,138以及较低介电常数的绝缘膜， 111,121,131,141，其层压以形成至少两层。 边界面包括位于互连侧面的绝缘膜。 版权所有（C）2006，JPO＆NCIPI