-
公开(公告)号：US20200075519A1
公开(公告)日：2020-03-05
申请号：US16553179
申请日：2019-08-28
Applicant: Industrial Technology Research Institute
Inventor： Yu-Min Lin , Ang-Ying Lin , Sheng-Tsai Wu , Tao-Chih Chang , Wei-Chung Lo
Abstract: A hetero-integrated structure includes a substrate, a die, a passivation layer, a first redistribution layer, a second redistribution layer, and connecting portions. The die is attached on the substrate. The die has an active surface and a non-active surface. The active surface has pads. The passivation layer covers sidewalls and a surface of the die to expose a surface of the pads. The first redistribution layer is located on the passivation layer and electrically connected to the pads. The second redistribution layer is located on the substrate and adjacent to the die. The connecting portions are connected to the first redistribution layer and the second redistribution layer.
-
12.发明授权公开(公告)号：US09448121B2
公开(公告)日：2016-09-20
申请号：US13854139
申请日：2013-04-01
Applicant: Industrial Technology Research Institute
Inventor： Heng-Chieh Chien , Ming-Ji Dai , Sheng-Tsai Wu , Huey-Lin Hsieh , Jing-Yi Huang
Abstract: A measurement method, a measurement apparatus, and a computer program product for measuring a thermoelectric module are provided. A temperature is provided to the thermoelectric module. A current is applied to the thermoelectric module to turn both sides of the thermoelectric module into a hot side and a cold side. The temperature of the hot side is higher than that of the cold side. A terminal voltage of the thermoelectric module, a hot side temperature of the hot side, and a cold side temperature of the cold side are measured at different time points. A thermoelectric relationship between the terminal voltages and differences between the hot side temperatures and the corresponding cold side temperatures is obtained according to the terminal voltages, the hot side temperatures, and the cold side temperatures. At least one first parameter of the thermoelectric module is estimated according to the thermoelectric relationship.
Abstract translation: 提供了一种用于测量热电模块的测量方法，测量装置和计算机程序产品。 向热电模块提供温度。 向热电模块施加电流以将热电模块的两侧转变成热侧和冷侧。 热侧的温度高于冷侧的温度。 在不同的时间点测量热电模块的端电压，热侧的热侧温度和冷侧的冷侧温度。 根据端子电压，热侧温度和冷侧温度，获得端子电压与热侧温度与相应的冷侧温度之间的差异的热电关系。 根据热电关系估计热电模块的至少一个第一参数。
-
公开(公告)号：US12074137B2
公开(公告)日：2024-08-27
申请号：US18166493
申请日：2023-02-09
Applicant: Industrial Technology Research Institute
Inventor： Yu-Min Lin , Ang-Ying Lin , Sheng-Tsai Wu , Chao-Jung Chen , Tzu-Hsuan Ni , Shin-Yi Huang , Yuan-Yin Lo
IPC: H01L21/56 , H01L23/31 , H01L23/538 , H01L25/00 , H01L25/065
CPC classification number: H01L25/0652 , H01L21/563 , H01L23/3128 , H01L23/5383 , H01L25/50 , H01L2225/06548 , H01L2924/181
Abstract: A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes a redistribution circuit structure; a first semiconductor chip disposed on the redistribution structure and having a first active surface on which a first conductive post is disposed; a second semiconductor chip disposed above the first semiconductor chip and having a second active surface on which a first conductor is disposed; and a first encapsulant disposed on the redistribution circuit structure and encapsulating at least the first semiconductor chip, wherein the first conductive post and the first conductor are aligned and bonded to each other to electrically connect the first semiconductor chip and the second semiconductor chip.
-
公开(公告)号：US11854961B2
公开(公告)日：2023-12-26
申请号：US17095744
申请日：2020-11-12
Inventor： Yu-Hua Chen , Wei-Chung Lo , Tao-Chih Chang , Yu-Min Lin , Sheng-Tsai Wu
IPC: H01L29/00 , H01L23/522 , H01L23/498 , H01L25/04 , H01L21/48
CPC classification number: H01L23/5226 , H01L21/4857 , H01L23/49822 , H01L23/49833 , H01L23/49838 , H01L25/04 , H01L2924/0002
Abstract: A package substrate includes a substrate, an insulating protective layer and an interposer. The substrate has a first surface and a second surface opposing to the first surface. The substrate includes a plurality of first conductive pads embedded in the first surface. The insulating protective layer is disposed on the first surface of the substrate. The insulating protective layer has an opening for exposing the first conductive pads embedded in the first surface of the substrate. The interposer has a top surface and a bottom surface opposing to the top surface. The interposer includes a plurality of conductive vias and a plurality of second conductive pads located on the bottom surface. The interposer is located in a recess defined by the opening of the insulating protective layer and the first surface of the substrate. Each of the second conductive pads is electrically connected to corresponding first conductive pad.
-
公开(公告)号：US11004816B2
公开(公告)日：2021-05-11
申请号：US16553179
申请日：2019-08-28
Applicant: Industrial Technology Research Institute
Inventor： Yu-Min Lin , Ang-Ying Lin , Sheng-Tsai Wu , Tao-Chih Chang , Wei-Chung Lo
IPC: H01L23/544 , H01L23/00 , H01L21/78 , H01L23/31
Abstract: A hetero-integrated structure includes a substrate, a die, a passivation layer, a first redistribution layer, a second redistribution layer, and connecting portions. The die is attached on the substrate. The die has an active surface and a non-active surface. The active surface has pads. The passivation layer covers sidewalls and a surface of the die to expose a surface of the pads. The first redistribution layer is located on the passivation layer and electrically connected to the pads. The second redistribution layer is located on the substrate and adjacent to the die. The connecting portions are connected to the first redistribution layer and the second redistribution layer.
-
Patent Agency Ranking
公开(公告)号：US20210118860A1
公开(公告)日：2021-04-22
申请号：US16884051
申请日：2020-05-27
Applicant: Industrial Technology Research Institute
Inventor： Sheng-Tsai Wu , Yu-Min Lin , Yuan-Yin Lo , Ang-Ying Lin , Tzu-Hsuan Ni , Chao-Jung Chen , Shin-Yi Huang
IPC: H01L25/18 , H01L31/0203 , H01L23/00
Abstract: An image sensor package and a manufacturing method thereof are provided. The image sensor package includes a redistribution circuit structure; an image sensing chip disposed on the redistribution circuit structure and having a sensing surface, on which a sensing area and a first conductive pillar arranged in the periphery of the sensing area are disposed; a lid covering the sensing area; an encapsulant disposed on the redistribution circuit structure and encapsulating at least part of the image sensing chip and the cover; and a top tier semiconductor chip disposed above the image sensing chip and having an active surface on which a first conductor is disposed. The first conductor overlaps the image sensing chip in a direction perpendicular to the sensing surface. The first conductive pillar and the first conductor are aligned and bonded to each other to electrically connect the image sensing chip and the top tier semiconductor chip.
-
公开(公告)号：US20230197680A1
公开(公告)日：2023-06-22
申请号：US17564197
申请日：2021-12-28
Applicant: Industrial Technology Research Institute
Inventor： Po-Kai Chiu , Sheng-Tsai Wu , Yu-Min Lin , Wen-Hung Liu , Ang-Ying Lin , Chang-Sheng Chen
IPC: H01L25/065 , H01L23/367 , H01L23/498 , H01L23/66 , H01L23/31 , H01L23/00
CPC classification number: H01L25/0652 , H01L23/367 , H01L23/49822 , H01L23/66 , H01L23/3107 , H01L23/49811 , H01L24/16 , H01L2223/6677 , H01L2224/16227
Abstract: An integrated antenna package structure includes a first redistribution structure, a first chip, a heat dissipation structure, a second chip, and an antenna structure. The first chip is located on a first side of the first redistribution structure, and is electrically connected to the first redistribution structure. The heat dissipation structure is thermally connected to the first chip, and the first chip is located between the heat dissipation structure and the first redistribution structure. The second chip is located on a second side of the first redistribution structure opposite to the first side, and is electrically connected to the first redistribution structure. The antenna structure is electrically connected to the first redistribution structure.
-
公开(公告)号：US20230187409A1
公开(公告)日：2023-06-15
申请号：US18166493
申请日：2023-02-09
Applicant: Industrial Technology Research Institute
Inventor： Yu-Min Lin , Ang-Ying Lin , Sheng-Tsai Wu , Chao-Jung Chen , Tzu-Hsuan Ni , Shin-Yi Huang , Yuan-Yin Lo
IPC: H01L25/065 , H01L23/31 , H01L25/00 , H01L21/56 , H01L23/538
CPC classification number: H01L25/0652 , H01L21/563 , H01L23/3128 , H01L23/5383 , H01L25/50 , H01L2225/06548
Abstract: A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes a redistribution circuit structure; a first semiconductor chip disposed on the redistribution structure and having a first active surface on which a first conductive post is disposed; a second semiconductor chip disposed above the first semiconductor chip and having a second active surface on which a first conductor is disposed; and a first encapsulant disposed on the redistribution circuit structure and encapsulating at least the first semiconductor chip, wherein the first conductive post and the first conductor are aligned and bonded to each other to electrically connect the first semiconductor chip and the second semiconductor chip.
-
公开(公告)号：US11646270B2
公开(公告)日：2023-05-09
申请号：US17065521
申请日：2020-10-08
Applicant: Industrial Technology Research Institute
Inventor： Ang-Ying Lin , Yu-Min Lin , Shin-Yi Huang , Sheng-Tsai Wu , Yuan-Yin Lo , Tzu-Hsuan Ni , Chao-Jung Chen
IPC: H01L23/538 , H01L21/48 , H01L23/00 , H01L23/31
CPC classification number: H01L23/5386 , H01L21/481 , H01L21/486 , H01L21/4857 , H01L23/5383 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/24 , H01L24/73 , H01L23/3185 , H01L2224/1357 , H01L2224/13609 , H01L2224/13611 , H01L2224/13613 , H01L2224/13639 , H01L2224/13644 , H01L2224/13647 , H01L2224/16225 , H01L2224/16505 , H01L2224/1703 , H01L2224/2402 , H01L2224/24101 , H01L2224/24137 , H01L2224/73204 , H01L2224/73209
Abstract: A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes: an interposer including a wiring structure and an interposer via electrically connected to the wiring structure; a plurality of semiconductor chips located on a first surface of the interposer and electrically connected to each other through the interposer; an encapsulant located on the first surface of the interposer and encapsulating at least a portion of the plurality of semiconductor chips; and a redistribution circuit structure located on a second surface of the interposer opposite to the first surface, wherein the plurality of semiconductor chips are electrically connected to the redistribution circuit structure through at least the interposer.
-
公开(公告)号：US20220130812A1
公开(公告)日：2022-04-28
申请号：US17568740
申请日：2022-01-05
Applicant: Industrial Technology Research Institute
Inventor： Sheng-Tsai Wu , Yu-Min Lin , Yuan-Yin Lo , Ang-Ying Lin , Tzu-Hsuan Ni , Chao-Jung Chen , Shin-Yi Huang
IPC: H01L25/18 , H01L23/00 , H01L31/0203
Abstract: An image sensor package and a manufacturing method thereof are provided. The image sensor package includes a redistribution circuit structure; an image sensing chip disposed on the redistribution circuit structure and having a sensing surface, on which a sensing area and a first conductive pillar arranged in the periphery of the sensing area are disposed; a lid covering the sensing area; an encapsulant disposed on the redistribution circuit structure and encapsulating at least part of the image sensing chip and the cover; and a top tier semiconductor chip disposed above the image sensing chip and having an active surface on which a first conductor is disposed. The first conductor overlaps the image sensing chip in a direction perpendicular to the sensing surface. The first conductive pillar and the first conductor are aligned and bonded to each other to electrically connect the image sensing chip and the top tier semiconductor chip.
-
-
-
-
-
-
-
-
-
Search Results
26
records
(took 0.031 seconds)
