公开(公告)号：DE10344354A1

公开(公告)日：2005-05-12

申请号：DE10344354

申请日：2003-09-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： DIAS VICTOR

IPC: H03M1/12 ,  H03M1/14 ,  H03M1/38 ,  H03M1/44

Abstract: The invention provides a clocked analog/digital converter for successive approximation which is designed using a jointly used amplifier and a dynamic range expansion facility by means of a special design for the comparison circuit in the first converter stage. The comparison circuits in the analog/digital converter allow decisions to be made for the further signal processing previously in a preceding time period. Two respective generator circuits in successive converter stages share one amplifier. This reduces the amount of space taken up and current drawn, increases the clock rate and simplifies signal processing for signals with high levels.

公开(公告)号：DE102004024645B4

公开(公告)日：2010-03-11

申请号：DE102004024645

申请日：2004-05-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： DIAS VICTOR

IPC: H03M1/66 ,  H03M1/06 ,  H03M3/00 ,  H03M7/00

Abstract: Method and device for reducing the signal images at the output of a digital/analog converter. In a method for reducing the signal images at the output of a digital/analog converter, a frequency hopping clock generator provides a digital data signal whose data rate is varied according to a frequency hopping method. The digital data signal is converted into an analog signal by a digital/analog converter, the conversion clock being varied according to the frequency hopping method.

公开(公告)号：DE102005015390B4

公开(公告)日：2009-05-28

申请号：DE102005015390

申请日：2005-04-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： DIAS VICTOR

IPC: H03M3/00 ,  H03M1/36

Abstract: An input network (5) assigns headings based on whether input signals (V1+,V1-) exceed quantization thresholds or not. A combiner (9) assigns the headings to comparators (COMP1-COMP8) based on a control signal (10). The comparators generate quantized signals at the outputs. An independent claim is also included for a sigma delta encoder.

公开(公告)号：DE102006007479A1

公开(公告)日：2007-08-30

申请号：DE102006007479

申请日：2006-02-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BURGER RICCIO ROBERTO ,  DIAS VICTOR

IPC: G05F1/613

Abstract: The controller has input (IN) for supplying an input potential (V in). An output (OUT) picks an output potential (VDD shunt). A voltage drop circuit switches between the input and the output potentials, where a voltage difference between the input potential and the output potential falls during the operation of the controller over the voltage drop circuit. A control unit (201) sets the current flowing through the voltage drop circuit or a threshold value depending on the input potential and/or a preset value for the threshold value.

公开(公告)号：DE102004024645A1

公开(公告)日：2005-12-15

申请号：DE102004024645

申请日：2004-05-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： DIAS VICTOR

IPC: H03M1/06 ,  H03M1/66 ,  H03M3/00 ,  H03M7/00

Abstract: Method and device for reducing the signal images at the output of a digital/analog converter. In a method for reducing the signal images at the output of a digital/analog converter, a frequency hopping clock generator provides a digital data signal whose data rate is varied according to a frequency hopping method. The digital data signal is converted into an analog signal by a digital/analog converter, the conversion clock being varied according to the frequency hopping method.

公开(公告)号：DE10331572A1

公开(公告)日：2005-02-03

申请号：DE10331572

申请日：2003-07-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： DIAS VICTOR ,  FENK JOSEF

IPC: H03M3/02 ,  H03M3/00

Abstract: The invention discloses a sigma-delta converter arrangement with a forward path including an amplifier and a quantizer with a clock input, and a feedback path with a D/A converter. The amplifier is coupled to an integrator which is in the form of a resonator with a tunable frequency and is actuated by a frequency synthesizer that also prescribes the clock rate of the quantizer. The synchronization between the quantizer and resonator results in highly accurate matching given inexpensive integratabiliy, which means that the sigma-delta converter is suitable for use in mobile radios, for example.