公开(公告)号：DE69802607D1

公开(公告)日：2002-01-10

申请号：DE69802607

申请日：1998-03-12

Applicant: SIEMENS AG ,  IBM

Inventor： FIEGL BERNHARD ,  GLASHAUSER WALTER ,  LEVY MAX G ,  NASTASI VICTOR R

IPC: H01L21/76 ,  H01L21/304 ,  H01L21/3105 ,  H01L21/762

公开(公告)号：DE69824481T2

公开(公告)日：2005-07-07

申请号：DE69824481

申请日：1998-04-23

Applicant: SIEMENS AG ,  IBM

Inventor： LEVY MAX GERALD ,  FIEGL BERNHARD ,  GLASHAUSER WALTER ,  PREIN FRANK

IPC: H01L21/76 ,  H01L21/304 ,  H01L21/306 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/108 ,  H01L21/8238

Abstract: FET devices (10) are manufactured using STI on a semiconductor substrate (11) coated with a pad (14) from which are formed raised active silicon device areas and dummy active silicon mesas (12) capped with pad structures on the doped silicon substrate and pad structure. A conformal blanket silicon oxide (22) layer is deposited on the device (10) with conformal projections above the mesas (12). Then a polysilicon film (24) on the blanket silicon oxide layer (22) is deposited with conformal projections above the mesas (12). The polysilicon film projections are removed in a CMP polishing step which continues until the silicon oxide layer (22) is exposed over the pad structures (14). Selective RIE partial etching of the conformal silicon oxide layer (22) over the mesas (12) is next, followed in turn by CMP planarization of the conformal blanket silicon oxide layer (22) which converts the silicon oxide layer into a planar silicon oxide layer, using the pad silicon nitride (14) as an etch stop.

公开(公告)号：DE69802607T2

公开(公告)日：2002-07-25

申请号：DE69802607

申请日：1998-03-12

Applicant: SIEMENS AG ,  IBM

Inventor： FIEGL BERNHARD ,  GLASHAUSER WALTER ,  LEVY MAX G ,  NASTASI VICTOR R

IPC: H01L21/76 ,  H01L21/304 ,  H01L21/3105 ,  H01L21/762

公开(公告)号：DE102004029355B4

公开(公告)日：2008-05-15

申请号：DE102004029355

申请日：2004-06-17

Applicant: IBM ,  QIMONDA AG

Inventor： COSTRINI GREG ,  GAIDIS MICHAEL C ,  RATH DAVID L ,  GLASHAUSER WALTER

IPC: H01L21/283 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/60

公开(公告)号：DE69824481D1

公开(公告)日：2004-07-22

申请号：DE69824481

申请日：1998-04-23

Applicant: SIEMENS AG ,  IBM

Inventor： LEVY MAX GERALD ,  FIEGL BERNHARD ,  GLASHAUSER WALTER ,  PREIN FRANK

IPC: H01L21/76 ,  H01L21/304 ,  H01L21/306 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/108 ,  H01L21/8238

Abstract: FET devices (10) are manufactured using STI on a semiconductor substrate (11) coated with a pad (14) from which are formed raised active silicon device areas and dummy active silicon mesas (12) capped with pad structures on the doped silicon substrate and pad structure. A conformal blanket silicon oxide (22) layer is deposited on the device (10) with conformal projections above the mesas (12). Then a polysilicon film (24) on the blanket silicon oxide layer (22) is deposited with conformal projections above the mesas (12). The polysilicon film projections are removed in a CMP polishing step which continues until the silicon oxide layer (22) is exposed over the pad structures (14). Selective RIE partial etching of the conformal silicon oxide layer (22) over the mesas (12) is next, followed in turn by CMP planarization of the conformal blanket silicon oxide layer (22) which converts the silicon oxide layer into a planar silicon oxide layer, using the pad silicon nitride (14) as an etch stop.