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    METHOD OF FILLING IN SHALLOW TRENCH
    2.
    发明专利
    METHOD OF FILLING IN SHALLOW TRENCH 失效

    公开(公告)号：JPH10294362A

    公开(公告)日：1998-11-04

    申请号：JP9896898

    申请日：1998-04-10

    Applicant: IBM ,  SIEMENS AG

    Inventor： FIEGL BERNHARD ,  GLASHAUSER WALTER ,  LEVY MAX G ,  NASTASI VICTOR R

    IPC: H01L21/76 ,  H01L21/304 ,  H01L21/3105 ,  H01L21/762

    Abstract: PROBLEM TO BE SOLVED: To enable a process through which a shallow trench is filled in to be enhanced in manufacturing properties and yield by a method wherein an intermediate plane layer is formed, and the lower layer of a thick oxide is selectively etched to deteriorate in planarity. SOLUTION: An upper planar surface is formed so as to be flush with the fill-in upper surface 115 of a fill-in layer 110. A polish stop layer 130 is removed by the use of etching chemicals which are capable of etching both the polish stop layer 130 and a temporary fill-in layer 120, and an intermediate plane surface is kept unremoved leaving the cover part of the temporary fill-in layer 120 unremoved. A part of the fill-in layer 110 located outside the cover part of the temporary fill-in layer 120 is etched as deep as a point shallower than a trench by the use of chemicals which etch the fill-in layer 110 preferentially so as to enable the fill-in upper surface 115 of the fill-in layer 110 located above a reference surface to be flush with the fill-in upper surface 115 of the fill-in layer 110 located in the trench, whereby a planar surface is deteriorated in flatness.

    4.
    发明专利
    未知

    公开(公告)号：DE69824481T2

    公开(公告)日：2005-07-07

    申请号：DE69824481

    申请日：1998-04-23

    Applicant: SIEMENS AG ,  IBM

    Inventor： LEVY MAX GERALD ,  FIEGL BERNHARD ,  GLASHAUSER WALTER ,  PREIN FRANK

    IPC: H01L21/76 ,  H01L21/304 ,  H01L21/306 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/108 ,  H01L21/8238

    Abstract: FET devices (10) are manufactured using STI on a semiconductor substrate (11) coated with a pad (14) from which are formed raised active silicon device areas and dummy active silicon mesas (12) capped with pad structures on the doped silicon substrate and pad structure. A conformal blanket silicon oxide (22) layer is deposited on the device (10) with conformal projections above the mesas (12). Then a polysilicon film (24) on the blanket silicon oxide layer (22) is deposited with conformal projections above the mesas (12). The polysilicon film projections are removed in a CMP polishing step which continues until the silicon oxide layer (22) is exposed over the pad structures (14). Selective RIE partial etching of the conformal silicon oxide layer (22) over the mesas (12) is next, followed in turn by CMP planarization of the conformal blanket silicon oxide layer (22) which converts the silicon oxide layer into a planar silicon oxide layer, using the pad silicon nitride (14) as an etch stop.

    6.
    发明专利
    未知

    公开(公告)号：DE69824481D1

    公开(公告)日：2004-07-22

    申请号：DE69824481

    申请日：1998-04-23

    Applicant: SIEMENS AG ,  IBM

    Inventor： LEVY MAX GERALD ,  FIEGL BERNHARD ,  GLASHAUSER WALTER ,  PREIN FRANK

    IPC: H01L21/76 ,  H01L21/304 ,  H01L21/306 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/108 ,  H01L21/8238

    Abstract: FET devices (10) are manufactured using STI on a semiconductor substrate (11) coated with a pad (14) from which are formed raised active silicon device areas and dummy active silicon mesas (12) capped with pad structures on the doped silicon substrate and pad structure. A conformal blanket silicon oxide (22) layer is deposited on the device (10) with conformal projections above the mesas (12). Then a polysilicon film (24) on the blanket silicon oxide layer (22) is deposited with conformal projections above the mesas (12). The polysilicon film projections are removed in a CMP polishing step which continues until the silicon oxide layer (22) is exposed over the pad structures (14). Selective RIE partial etching of the conformal silicon oxide layer (22) over the mesas (12) is next, followed in turn by CMP planarization of the conformal blanket silicon oxide layer (22) which converts the silicon oxide layer into a planar silicon oxide layer, using the pad silicon nitride (14) as an etch stop.

    PROCESS FOR THE PRODUCTION OF AN X-RAY MASK WITH A METALLIC SUPPORT FOIL
    9.
    发明专利
    PROCESS FOR THE PRODUCTION OF AN X-RAY MASK WITH A METALLIC SUPPORT FOIL 未知

    公开(公告)号：DE3466088D1

    公开(公告)日：1987-10-15

    申请号：DE3466088

    申请日：1984-10-16

    Applicant: SIEMENS AG

    Inventor： GLASHAUSER WALTER

    IPC: G03F1/00 ,  G03F1/22 ,  H01L21/027

    Abstract: A method for constructing an x-ray mask having a metal carrier foil supporting an x-ray absorbing structure on a metal frame characterized by providing a carrier plate coated with a nickel layer on which a carrier foil is deposited, then forming an electrodepositing mask on the carrier foil with portions of the carrier foil being exposed, electroplating gold onto the exposed portions and subsequently etching the carrier plate to form a window therein and then etching the exposed nickel layer to at least expose the surface of portions of the carrier foil.

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