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公开(公告)号：US10608177B2
公开(公告)日：2020-03-31
申请号：US15525200
申请日：2014-12-26
Inventor： Hangbing Lv , Ming Liu , Qi Liu , Shibing Long
Abstract: The present disclosure discloses a self-gated RRAM cell and a manufacturing method thereof; which belong to the field of microelectronic technology. The self-gated RRAM cell comprises: a stacked structure containing multiple layers of conductive lower electrodes; a vertical trench formed by etching the stacked structure; a M8XY6 gated layer formed on an inner wall and a bottom of the vertical trench; a resistance transition layer formed on a surface of the M8XY6, gated layer; and a conductive upper electrode formed on a surface of the resistance transition layer, the vertical trench being filled with the conductive upper electrode. The present disclosure is implemented on a basis of using the self-gated RRAM as a memory cell. It may not depend on a gated transistor and a diode, but relies on a non-linear variation characteristic of resistance of its own varied with voltage to achieve a self-gated function, which has a simple structure, easy integration, high density and low cost, capable of suppressing a reading crosstalk phenomenon in a cross array structure; and is also adapted for a planar stacked cross array structure and a vertical cross array structure, achieving 3D storage with a high density.
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公开(公告)号：US10134983B2
公开(公告)日：2018-11-20
申请号：US15546212
申请日：2015-05-14
Inventor： Qi Liu , Ming Liu , Haitao Sun , Keke Zhang , Shibing Long , Hangbing Lv , Writam Banerjee , Kangwei Zhang
IPC: H01L45/00
Abstract: A nonvolatile resistive switching memory, comprising an inert metal electrode, a resistive switching functional layer, and an easily oxidizable metal electrode, and characterized in that: a graphene barrier layer is inserted between the inert metal electrode and the resistive switching functional layer, which is capable of preventing the easily oxidizable metal ions from migrating into the inert metal electrode through the resistive switching functional layer under the action of electric field during the programming of the device. The manufacturing method therefore comprises adding a monolayer or multilayer graphene thin film between the inert electrode and the solid-state electrolyte resistive switching functional layer which services as a metal ion barrier layer to stop electrically-conductive metal filaments formed in the resistive switching layer from diffusing into the inert electrode layer during a RRAM device programming process, eliminating erroneous programming phenomenon occurring during the erasing process, improving device reliability.
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Patent Agency Ranking
公开(公告)号：US11245074B2
公开(公告)日：2022-02-08
申请号：US16616785
申请日：2017-05-26
Inventor： Hangbing Lv , Ming Liu , Shibing Long , Qi Liu
Abstract: A RRAM and a method for fabricating the same, wherein the RRAM comprises: a bottom electrode; an oxide layer containing a bottom electrode metal, disposed on the bottom electrode; a resistance-switching layer, disposed on the oxide layer containing a bottom electrode metal, wherein the resistance-switching layer material is a nitrogen-containing tantalum oxide; an inserting layer, disposed on the resistance-switching layer, wherein the inserting layer material comprises a metal or a semiconductor; a top electrode, disposed on the inserting layer. By providing the to resistance-switching layer with a nitrogen-containing tantalum oxide, compared with Ta2O5, the RRAM of the present disclosure has a low activation voltage and a high on-off ratio, and can enhance the control capability over the device resistance by the number of oxygen vacancies.
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公开(公告)号：US10418549B2
公开(公告)日：2019-09-17
申请号：US16064116
申请日：2016-08-12
Inventor： Nianduan Lu , Pengxiao Sun , Ling Li , Ming Liu , Qi Liu , Hangbing Lv , Shibing Long
Abstract: A method for evaluating the thermal effects of 3D RRAM arrays and reducing thermal crosstalk, including the following steps: Step 1: calculating the temperature distribution in the array through 3D Fourier heat conduction equation; Step 2, selecting a heat transfer mode; Step 3, selecting an appropriate array structure; Step 4, analyzing the effect of position of programming device in the array on the temperature; Step 5, analyzing the thermal crosstalk effect in the array; Step 6, evaluating thermal effects and thermal crosstalk; Step 7, changing the array structure or modify operating parameters based on the evaluation results to reduce the thermal crosstalk. According to the method of the present invention, the influence of the position of the device on the temperature is analyzed according to the heat transfer mode of the 3D RRAM array, the thermal effect and the thermal crosstalk are evaluated, and the appropriate array structure and operating parameters are selected according to the evaluation result, which effectively improves the thermal stability of the device.
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公开(公告)号：US10297748B2
公开(公告)日：2019-05-21
申请号：US15539608
申请日：2014-12-26
Inventor： Hangbing Lv , Ming Liu , Qi Liu , Shibing Long
Abstract: There is provided a three-terminal atomic switching device and a method of manufacturing the same, which belongs to the field of microelectronics manufacturing and memory technology. The three-terminal atomic switching device includes: a stack structure including a source terminal and a drain terminal; a vertical trench formed by etching the stack structure; an M8XY6 channel layer formed on an inner wall and a bottom of the vertical trench; and a control terminal formed on a surface of the M8XY6 channel layer, wherein the control terminal fills the vertical trench. The source terminal resistance and the drain terminal resistance are controlled by the control terminal. The invention is based on the three-terminal atomic switching device, and realizes high switching ratio characteristic, simple structure, easy integration, high density and low cost due to high non-linearity of the source-drain resistance with respect to the control terminal voltage, and thus can be used in a gated device in a cross-array structure to inhibit a crosstalk phenomenon caused by the leakage current. The three-terminal atomic switching device proposed by the invention is suitable for a planar stacked cross-array structure and a vertical cross-array structure, so as to realize high-density three-dimensional storage.
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公开(公告)号：US20180026183A1
公开(公告)日：2018-01-25
申请号：US15546212
申请日：2015-05-14
Inventor： Qi Liu , Ming Liu , Haitao Sun , Keke Zhang , Shibing Long , Hangbing Lv , Writam Banerjee , Kangwei Zhang
IPC: H01L45/00
CPC classification number: H01L45/1246 , H01L45/08 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/142 , H01L45/143 , H01L45/146 , H01L45/16
Abstract: A nonvolatile resistive switching memory, comprising an inert metal electrode, a resistive switching functional layer, and an easily oxidizable metal electrode, and characterized in that: a graphene barrier layer is inserted between the inert metal electrode and the resistive switching functional layer, which is capable of preventing the easily oxidizable metal ions from migrating into the inert metal electrode through the resistive switching functional layer under the action of electric field during the programming of the device. The manufacturing method therefore comprises adding a monolayer or multilayer graphene thin film between the inert electrode and the solid-state electrolyte resistive switching functional layer which services as a metal ion barrier layer to stop electrically-conductive metal filaments formed in the resistive switching layer from diffusing into the inert electrode layer during a RRAM device programming process, eliminating erroneous programming phenomenon occurring during the erasing process, improving device reliability.
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公开(公告)号：US20180019393A1
公开(公告)日：2018-01-18
申请号：US15546218
申请日：2015-05-14
Inventor： Qi Liu , Ming Liu , Haltao Sun , Hangbing Lv , Shibing Long , Writam Banerjee , Kangwei Zhang
IPC: H01L45/00
CPC classification number: H01L45/143 , H01L45/085 , H01L45/1233 , H01L45/1253 , H01L45/1266 , H01L45/144 , H01L45/146 , H01L45/1608
Abstract: A nonvolatile resistive switching memory includes an inert metal electrode, a resistive switching functional layer, and an easily oxidizable metal electrode. A graphene intercalation layer with nanopores, interposed between the easily oxidizable metal electrode and the resistive switching functional layer, is capable of controlling the metal ions, which are formed by the oxidation of the easily oxidizable metal electrode during the programming of the device, and only enter into the resistive switching functional layer through the position of the nanopores. Further, the graphene intercalation layer with nanopores is capable of blocking the diffusion of the metal ions, making the metal ions, which are formed after the oxidation of the easily oxidizable metal electrode, enter into the resistive switching functional layer only through the position of the nanopores during the programming of the device, thereby controlling the growing position of conductive filament.
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