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公开(公告)号：US10312439B2
公开(公告)日：2019-06-04
申请号：US15546218
申请日：2015-05-14
Inventor： Qi Liu , Ming Liu , Haltao Sun , Hangbing Lv , Shibing Long , Writam Banerjee , Kangwei Zhang
IPC: H01L45/00
Abstract: A nonvolatile resistive switching memory includes an inert metal electrode, a resistive switching functional layer, and an easily oxidizable metal electrode. A graphene intercalation layer with nanopores, interposed between the easily oxidizable metal electrode and the resistive switching functional layer, is capable of controlling the metal ions, which are formed by the oxidation of the easily oxidizable metal electrode during the programming of the device, and only enter into the resistive switching functional layer through the position of the nanopores. Further, the graphene intercalation layer with nanopores is capable of blocking the diffusion of the metal ions, making the metal ions, which are formed after the oxidation of the easily oxidizable metal electrode, enter into the resistive switching functional layer only through the position of the nanopores during the programming of the device, thereby controlling the growing position of conductive filament.
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2.发明申请公开(公告)号：US20180366643A1
公开(公告)日：2018-12-20
申请号：US16064116
申请日：2016-08-12
Inventor： Nianduan Lu , Pengxiao Sun , Ling Li , Ming Iiu , Qi Liu , Hangbing Lv , Shibing Long
CPC classification number: H01L45/128 , G01N25/20 , G11C7/04 , G11C13/0002 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2481 , H01L45/00 , H01L45/04 , H01L45/1233 , H01L45/1293
Abstract: A method for evaluating the thermal effects of 3D RRAM arrays and reducing thermal crosstalk, including the following steps: Step 1: calculating the temperature distribution in the array through 3D Fourier heat conduction equation; Step 2, selecting a heat transfer mode; Step 3, selecting an appropriate array structure; Step 4, analyzing the effect of position of programming device in the array on the temperature; Step 5, analyzing the thermal crosstalk effect in the array; Step 6, evaluating thermal effects and thermal crosstalk; Step 7, changing the array structure or modify operating parameters based on the evaluation results to reduce the thermal crosstalk. According to the method of the present invention, the influence of the position of the device on the temperature is analyzed according to the heat transfer mode of the 3D RRAM array, the thermal effect and the thermal crosstalk are evaluated, and the appropriate array structure and operating parameters are selected according to the evaluation result, which effectively improves the thermal stability of the device.
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公开(公告)号：US20170331034A1
公开(公告)日：2017-11-16
申请号：US15525200
申请日：2014-12-26
Inventor： Hangbing Lv , Ming Liu , Qi Liu , Shibing Long
CPC classification number: H01L45/1253 , H01L27/24 , H01L27/249 , H01L45/04 , H01L45/12 , H01L45/1226 , H01L45/14 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/1608
Abstract: The present disclosure discloses a self-gated RRAM cell and a manufacturing method thereof; which belong to the field of microelectronic technology. The self-gated RRAM cell comprises: a stacked structure containing multiple layers of conductive lower electrodes; a vertical trench formed by etching the stacked structure; a M8XY6 gated layer formed on an inner wall and a bottom of the vertical trench; a resistance transition layer formed on a surface of the M8XY6, gated layer; and a conductive upper electrode formed on a surface of the resistance transition layer, the vertical trench being filled with the conductive upper electrode. The present disclosure is implemented on a basis of using the self-gated RRAM as a memory cell. It may not depend on a gated transistor and a diode, but relies on a non-linear variation characteristic of resistance of its own varied with voltage to achieve a self-gated function, which has a simple structure, easy integration, high density and low cost, capable of suppressing a reading crosstalk phenomenon in a cross array structure; and is also adapted for a planar stacked cross array structure and a vertical cross array structure, achieving 3D storage with a high density.
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公开(公告)号：US20210295143A1
公开(公告)日：2021-09-23
申请号：US17250569
申请日：2018-08-07
Inventor： Qi Liu , Xumeng Zhang , Ming Liu , Hangbing Lv , Shibing Long
Abstract: A neuron circuit (100), including a memristive element (M1), a trigger element (D1), a feedback element (T1) and an AND circuit (A1). The memristive element (M1) is used to receive an excitation signal. The trigger element (D1) is connected to the memristive element (M1) and is used to receive a clock control signal for the neuron circuit and an output signal of the memristive element (M1). The feedback element (T1) is connected to an output end of the trigger element (D1) and an input end of the memristive element (M1) and is used to control a voltage at the input end of the memristive element (M1). The AND circuit (A1) is used to perform an AND operation on an output signal of the trigger element (D1) and the clock control signal. An output signal of the AND circuit (A1) acts as an output signal of the neuron circuit (100).
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5.发明授权公开(公告)号：US09508776B2
公开(公告)日：2016-11-29
申请号：US14771145
申请日：2013-09-24
Inventor： Qi Liu , Ming Liu , Shibing Long , Hangbing Lv , Yan Wang
CPC classification number: H01L27/2463 , G11C13/0007 , G11C13/0023 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2013/0073 , G11C2213/15 , H01L27/2409 , H01L45/04 , H01L45/08 , H01L45/124 , H01L45/1253 , H01L45/146 , H01L45/148
Abstract: A gating device cell for a cross array of bipolar resistive memory cells comprises an n-p diode and a p-n diode, wherein the n-p diode and the p-n diode have opposite polarities and are connected in parallel, such that the gating device cell exhibits a bidirectional rectification feature. The gating device cell exhibits the bidirectional rectification feature, that is, it can provide a relatively high current density at any voltage polarity in its ON state, and also a relatively great rectification ratio (Rv/2/RV) under a read voltage. Therefore, it is possible to suppress read crosstalk in the cross array of bipolar resistive memory cells to avoid misreading, thereby solving the problem that a conventional rectifier diode is only applicable to a cross array of unipolar resistive memory cells.
Abstract translation: 用于双极性电阻式存储单元的交叉阵列的门控器件单元包括np二极管和pn二极管，其中np二极管和pn二极管具有相反的极性并且并联连接，使得门控器件单元呈现双向整流特征 。 选通装置单元具有双向整流特征，即，其可以在其导通状态下的任何电压极性下提供相对高的电流密度，并且在读取电压下可以提供相对较大的整流比（Rv / 2 / RV）。 因此，可以抑制双极电阻存储单元的交叉阵列中的读串扰，以避免误读，从而解决了传统的整流二极管仅可应用于单极性电阻存储单元的交叉阵列的问题。
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Patent Agency Ranking
公开(公告)号：US11223013B2
公开(公告)日：2022-01-11
申请号：US16489266
申请日：2017-02-28
Inventor： Qi Liu , Xiaolong Zhao , Sen Liu , Ming Liu , Hangbing Lv , Shibing Long , Yan Wang , Facai Wu
IPC: H01L45/00
Abstract: The present disclosure provides a conductive bridge semiconductor device and a method of manufacturing the same. The conductive bridge semiconductor device includes a lower electrode, a resistive switching functional layer, an ion barrier layer and an active upper electrode from bottom to top, wherein the ion barrier layer is provided with certain holes through which active conductive ions pass. Based on this structure, the precise designing of the holes on the barrier layer facilitates the modulation of the quantity, size and density of the conduction paths in the conductive bridge semiconductor device, which enables that the conductive bridge semiconductor device can be modulated to be a nonvolatile conductive bridge resistive random access memory or a volatile conductive bridge selector. Based on the above method, ultra-low power nonvolatile conductive bridge memory and high driving-current volatile conductive bridge selector with controllable polarity are completed.
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公开(公告)号：US10665780B2
公开(公告)日：2020-05-26
申请号：US16085400
申请日：2016-03-18
Inventor： Ming Liu , Qing Luo , Xiaoxin Xu , Hangbing Lv , Shibing Long , Qi Liu
Abstract: A selector for a bipolar resistive random access memory and a method for fabricating the selector are provided. The method includes: providing a substrate; forming a lower electrode on the substrate, where the lower electrode is made of a metal, and the metal is made up of metal atoms which diffuse under an annealing condition of below 400° C.; forming a first metal oxide layer on the lower electrode; performing an annealing process on the first metal oxide layer to make the metal atoms in the lower electrode diffuse into the first metal oxide layer to form a first metal oxide layer doped with metal atoms; forming a second metal oxide layer on the first metal oxide layer doped with metal atoms; forming an upper electrode layer on the second metal oxide layer; and patterning the upper electrode layer to form an upper electrode.
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公开(公告)号：US09779836B2
公开(公告)日：2017-10-03
申请号：US15125326
申请日：2014-03-12
Inventor： Chong Bi , Shibing Long , Ming Liu
CPC classification number: G11C19/0858 , G11C11/1675 , G11C11/18 , G11C11/5607 , G11C19/0808 , G11C19/0816 , G11C19/0825 , G11C19/0841 , G11C19/085
Abstract: The present disclosure relates to the technical field of information data storage and processing. There is provided a method for regulating magnetic multi-domain state, comprising: when a current is applied to a magnetic thin film, applying an additional external magnetic field having a magnetic field strength of 0 to 4×105 A/m to regulate magnetization state of the magnetic thin film; wherein the current is configured to drive movements of a magnetic domain of the magnetic multi-domain states in the magnetic thin film, and the external magnetic field is configured to regulate generation of new magnetic domain in the magnetic thin film and state of the magnetic domain during the movement, so that the magnetic thin film is in a stable magnetic multi-domain state. Such a multi-domain state can't be affected by a higher or lower current and keeps stable when the current is removed. Such a method may be used for magnetic memory or spin-logic device to implement a nonvolatile multi-valued storage, multi-bits logic operation, or neuromorphic computing.
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公开(公告)号：US20170092374A1
公开(公告)日：2017-03-30
申请号：US15125326
申请日：2014-03-12
Inventor： Chong Bi , Shibing Long , Ming Liu
IPC: G11C19/08
CPC classification number: G11C19/0858 , G11C11/1675 , G11C11/18 , G11C11/5607 , G11C19/0808 , G11C19/0816 , G11C19/0825 , G11C19/0841 , G11C19/085
Abstract: The present disclosure relates to the technical field of information data storage and processing. There is provided a method for regulating magnetic multi-domain state, comprising: when a current is applied to a magnetic thin film, applying an external magnetic field having a magnetic field strength of 0 to 4×105 A/m to regulate magnetization state of the magnetic thin film; wherein the current is configured to drive movements of a magnetic domain of the magnetic multi-domain states in the magnetic thin film, and the external magnetic field is configured to regulate generation of new magnetic domain in the magnetic thin film and state of the magnetic domain during the movement, so that the magnetic thin film is in a stable magnetic multi-domain state. Such a multi-domain state can't be affected by a higher or lower current and may be kept to be stable when the current is removed. Such a method may be used for current magnetic memory and to operate the magnetization stage of the spin-logic device in the future to implement a nonvolatile multi-valued storage and multi-bits logic operation.
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10.发明授权公开(公告)号：US11189345B2
公开(公告)日：2021-11-30
申请号：US16959225
申请日：2018-01-22
Inventor： Qi Liu , Wei Wang , Sen Liu , Feng Zhang , Hangbing Lv , Shibing Long , Ming Liu
Abstract: An operation method for integrating logic calculations and data storage based on a crossbar array structure of resistive switching devices. The calculation and storage functions of the method are based on the same hardware architecture, and the data storage is completed while performing calculation, thereby realizing the fusion of calculation and storage. The method includes applying a pulse sequence to a specified word line or bit line by a controller, configuring basic units of resistive switching devices to form different serial-parallel structures, such that three basic logic operations, i.e. NAND, OR, and COPY, are implemented and mutually combined on this basis, thereby implementing 16 types of binary Boolean logic and full addition operations, and on this basis, a method for implementing a parallel logic and full addition operations is provided.
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