公开(公告)号：US20220130820A1

公开(公告)日：2022-04-28

申请号：US17572437

申请日：2022-01-10

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Ilya Karpov ,  Brian Doyle ,  Ravi Pillarisetty ,  Abhishek Sharma

IPC: H01L27/02 ,  H01L29/861

Abstract: A backend electrostatic discharge (ESD) diode device structure is presented comprising: a first structure comprising a first material, wherein the first material includes metal; a second structure adjacent to the first structure, wherein the second structure comprises a second material, wherein the second material includes a semiconductor or an oxide; and a third structure adjacent to the second structure, wherein the third structure comprises the first material, wherein the second structure is between the first and third structures.

公开(公告)号：US11264317B2

公开(公告)日：2022-03-01

申请号：US15942999

申请日：2018-04-02

Applicant: Intel Corporation

Inventor： Vincent Dorgan ,  Jeffrey Hicks ,  Miriam Reshotko ,  Abhishek Sharma ,  Ilan Tsameret

IPC: H01L23/50 ,  H01L23/48 ,  H01L29/51 ,  G11C17/16 ,  H01L21/82 ,  H01L23/522 ,  H01L23/525 ,  H01L23/498

Abstract: Embodiments herein may describe techniques for an integrated circuit including a metal interconnect above a substrate, an interlayer dielectric (ILD) layer above the metal interconnect with an opening to expose the metal interconnect at a bottom of the opening. A dielectric layer may conformally cover sidewalls and the bottom of the opening and in contact with the metal interconnect. An electrode may be formed within the opening, above the metal interconnect, and separated from the metal interconnect by the dielectric layer. After a programming voltage may be applied between the metal interconnect and the electrode to generate a current between the metal interconnect and the electrode, a conductive path may be formed through the dielectric layer to couple the metal interconnect and the electrode, changing the resistance between the metal interconnect and the electrode. Other embodiments may be described and/or claimed.

公开(公告)号：US11222885B2

公开(公告)日：2022-01-11

申请号：US15940899

申请日：2018-03-29

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Ilya Karpov ,  Brian Doyle ,  Ravi Pillarisetty ,  Abhishek Sharma

IPC: H01L27/02 ,  H01L29/861

Abstract: A backend electrostatic discharge (ESD) diode device structure is presented comprising: a first structure comprising a first material, wherein the first material includes metal; a second structure adjacent to the first structure, wherein the second structure comprises a second material, wherein the second material includes a semiconductor or an oxide; and a third structure adjacent to the second structure, wherein the third structure comprises of the first material, wherein the second structure is between the first and third structures. Other embodiments are also disclosed and claimed.

公开(公告)号：US11211489B2

公开(公告)日：2021-12-28

申请号：US16650793

申请日：2017-12-27

Applicant: Intel Corporation

Inventor： Brian Doyle ,  Abhishek Sharma ,  Elijah Karpov ,  Ravi Pillarisetty ,  Prashant Majhi

IPC: H01L29/78 ,  H01L29/66

Abstract: Low resistance field-effect transistors and methods of manufacturing the same are disclosed herein. An example field-effect transistor disclosed herein includes a substrate and a stack above the substrate. The stack includes an insulator and a gate electrode. The example field-effect transistor includes a semiconductor material layer in a cavity in the stack. In the example field-effect transistor, a region of the semiconductor material layer proximate to the insulator is doped with a material of the insulator.

公开(公告)号：US11171243B2

公开(公告)日：2021-11-09

申请号：US16455581

申请日：2019-06-27

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Abhishek Sharma ,  Van Le ,  Jack Kavalieros ,  Shriram Shivaraman ,  Seung Hoon Sung ,  Tahir Ghani ,  Arnab Sen Gupta ,  Nazila Haratipour ,  Justin Weber

IPC: H01L29/786 ,  H01L29/221 ,  H01L21/8238 ,  H01L27/092

Abstract: Transistor structures may include a metal oxide contact buffer between a portion of a channel material and source or drain contact metallization. The contact buffer may improve control of transistor channel length by limiting reaction between contact metallization and the channel material. The channel material may be of a first composition and the contact buffer may be of a second composition.

公开(公告)号：US11121073B2

公开(公告)日：2021-09-14

申请号：US15943565

申请日：2018-04-02

Applicant: Intel Corporation

Inventor： Travis Lajoie ,  Abhishek Sharma ,  Juan Alzate-Vinasco ,  Chieh-Jen Ku ,  Shem Ogadhoh ,  Allen Gardiner ,  Blake Lin ,  Yih Wang ,  Pei-Hua Wang ,  Jack T. Kavalieros ,  Bernhard Sell ,  Tahir Ghani

IPC: H01L23/522 ,  H01L49/02 ,  H01L27/108 ,  H01L23/532

Abstract: An interconnect structure is disclosed. The interconnect structure includes a first metal interconnect in a bottom dielectric layer, a via that extends through a top dielectric layer, a metal plate, an intermediate dielectric layer, and an etch stop layer, and a metal in the via to extend through the top dielectric layer, the metal plate, the intermediate dielectric layer and the etch stop layer to the top surface of the first metal interconnect. The metal plate is coupled to an MIM capacitor that is parallel to the via. The second metal interconnect is on top of the metal in the via.

公开(公告)号：US11048434B2

公开(公告)日：2021-06-29

申请号：US16147024

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Raghavan Kumar ,  Phil Knag ,  Gregory K. Chen ,  Huseyin Ekin Sumbul ,  Sasikanth Manipatruni ,  Amrita Mathuriya ,  Abhishek Sharma ,  Ram Krishnamurthy ,  Ian A. Young

IPC: G11C11/419 ,  G06F3/06 ,  G04F10/00 ,  G11C13/00 ,  G11C11/418 ,  G11C7/10 ,  G11C11/54

Abstract: A memory circuit has compute-in-memory (CIM) circuitry that performs computations based on time-to-digital conversion (TDC). The memory circuit includes an array of memory cells addressable with column address and row address. The memory circuit includes CIM sense circuitry to sense a voltage for multiple memory cells triggered together. The CIM sense circuitry including a TDC circuit to convert a time for discharge of the multiple memory cells to a digital value. A processing circuit determines a value of the multiple memory cells based on the digital value.

公开(公告)号：US10956813B2

公开(公告)日：2021-03-23

申请号：US16147109

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Ian A. Young ,  Ram Krishnamurthy ,  Sasikanth Manipatruni ,  Gregory K. Chen ,  Amrita Mathuriya ,  Abhishek Sharma ,  Raghavan Kumar ,  Phil Knag ,  Huseyin Ekin Sumbul

IPC: G06N3/06 ,  G06N3/063 ,  G11C11/419 ,  G11C5/06 ,  H03M7/30 ,  G11C11/413 ,  G11C7/10 ,  G11C11/54 ,  G06N3/04

Abstract: An apparatus is described. The apparatus includes a compute in memory circuit. The compute in memory circuit includes a memory circuit and an encoder. The memory circuit is to provide 2m voltage levels on a read data line where m is greater than 1. The memory circuit includes storage cells sufficient to store a number of bits n where n is greater than m. The encoder is to receive an m bit input and convert the m bit input into an n bit word that is to be stored in the memory circuit, where, the m bit to n bit encoding performed by the encoder creates greater separation between those of the voltage levels that demonstrate wider voltage distributions on the read data line than others of the voltage levels.

公开(公告)号：US20200083359A1

公开(公告)日：2020-03-12

申请号：US16613751

申请日：2017-06-29

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Abhishek Sharma ,  Van H. Le ,  Gilbert Dewey ,  Willy Rachmady

IPC: H01L29/76 ,  H01L29/786 ,  H01L29/78 ,  H01L21/02

Abstract: Embodiments related to transistors having one or more non-planar transition metal dichalcogenide cladding layers, integrated circuits and systems incorporating such transistors, and methods for fabricating them are discussed.

公开(公告)号：US20190102359A1

公开(公告)日：2019-04-04

申请号：US16147036

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Phil KNAG ,  Gregory K. CHEN ,  Raghavan KUMAR ,  Huseyin Ekin SUMBUL ,  Abhishek Sharma ,  Sasikanth Manipatruni ,  Amrita Mathuriya ,  Ram A. Krishnamurthy ,  Ian A. Young

IPC: G06F17/16 ,  G11C11/419 ,  G11C11/418 ,  G11C7/10 ,  G06F9/30 ,  G11C11/56

Abstract: A binary CIM circuit enables all memory cells in a memory array to be effectively accessible simultaneously for computation using fixed pulse widths on the wordlines and equal capacitance on the bitlines. The fixed pulse widths and equal capacitance ensure that a minimum voltage drop in the bitline represents one least significant bit (LSB) so that the bitline voltage swing remains safely within the maximum allowable range. The binary CIM circuit maximizes the effective memory bandwidth of a memory array for a given maximum voltage range of bitline voltage.