公开(公告)号：US20240105854A1

公开(公告)日：2024-03-28

申请号：US18528545

申请日：2023-12-04

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Abhishek Sharma ,  Van Le ,  Jack Kavalieros ,  Shriram Shivaraman ,  Seung Hoon Sung ,  Tahir Ghani ,  Arnab Sen Gupta ,  Nazila Haratipour ,  Justin Weber

IPC: H01L29/786 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/221

CPC classification number: H01L29/7869 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/221 ,  H01L29/78696

Abstract: Transistor structures may include a metal oxide contact buffer between a portion of a channel material and source or drain contact metallization. The contact buffer may improve control of transistor channel length by limiting reaction between contact metallization and the channel material. The channel material may be of a first composition and the contact buffer may be of a second composition.

公开(公告)号：US20240008251A1

公开(公告)日：2024-01-04

申请号：US17856866

申请日：2022-07-01

Applicant: Intel Corporation

Inventor： Abhishek Sharma ,  Tahir Ghani ,  Wilfred Gomes ,  Anand Murthy

IPC: H01L27/108 ,  H01L23/427

CPC classification number: H01L27/10805 ,  H01L23/427 ,  H01L27/10897 ,  H01L27/1085 ,  H01L27/10873

Abstract: Integrated circuit dies, systems, and techniques are described herein related to one transistor-one capacitor dynamic random access memory. A memory device includes vertically aligned transistors having annular semiconductor structures and a shared bit line extending through the annular semiconductor structures, and vertically aligned capacitors having annular first capacitor plates, annular capacitor dielectric structures, and a shared second capacitor plate extending through the annular first capacitor plates, such that the annular first capacitor plates are in contact with corresponding ones of the annular semiconductor structures.

公开(公告)号：US11683929B2

公开(公告)日：2023-06-20

申请号：US17840186

申请日：2022-06-14

Applicant: Intel Corporation

Inventor： Travis W. Lajoie ,  Abhishek Sharma ,  Van H. Le ,  Chieh-Jen Ku ,  Pei-Hua Wang ,  Jack T. Kavalieros ,  Bernhard Sell ,  Tahir Ghani ,  Juan Alzate Vinasco

IPC: H01L21/82 ,  H10B12/00 ,  H01L29/786 ,  H01L29/66 ,  H01L29/49 ,  H01L21/311 ,  H01L21/822 ,  H01L21/8234

CPC classification number: H10B12/33 ,  H01L21/31111 ,  H01L21/8221 ,  H01L21/823487 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78642 ,  H01L29/78663 ,  H01L29/78672 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78693 ,  H01L29/78696 ,  H10B12/036 ,  H10B12/05

Abstract: Embodiments herein describe techniques for a semiconductor device including a capacitor and a transistor above the capacitor. A contact electrode may be shared between the capacitor and the transistor. The capacitor includes a first plate above a substrate, and the shared contact electrode above the first plate and separated from the first plate by a capacitor dielectric layer, where the shared contact electrode acts as a second plate for the capacitor. The transistor includes a gate electrode above the substrate and above the capacitor; a channel layer separated from the gate electrode by a gate dielectric layer, and in contact with the shared contact electrode; and a source electrode above the channel layer, separated from the gate electrode by the gate dielectric layer, and in contact with the channel layer. The shared contact electrode acts as a drain electrode of the transistor. Other embodiments may be described and/or claimed.

公开(公告)号：US11574910B2

公开(公告)日：2023-02-07

申请号：US16457677

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Abhishek Sharma ,  Willy Rachmady ,  Van H. Le ,  Travis W. Lajoie ,  Urusa Alaan ,  Hui Jae Yoo ,  Sean Ma ,  Aaron Lilak

IPC: H01L27/108 ,  H01L21/764 ,  H01L27/12

Abstract: A device is disclosed. The device includes a plurality of capacitors, a transistor connected to each of the plurality of capacitors, and a first dielectric layer and a second dielectric layer on respective adjacent sides of adjacent capacitors of the plurality of capacitors. The first dielectric layer and the second dielectric layer include a top portion and a bottom portion, the top portion of the first dielectric layer and the top portion of the second dielectric layer extend from respective directions and meet at a top portion of a space between the adjacent capacitors, the bottom portion of the first dielectric layer and the bottom portion of the second dielectric layer extend from respective directions and meet at a bottom portion of a space between the adjacent capacitors. The device also includes one or more air-gaps surrounded by the first dielectric layer and the second dielectric layer on respective adjacent sides of the adjacent capacitors, the top portion of the first dielectric layer and the second dielectric layer between the adjacent capacitors, and the bottom portion of the first dielectric layer and the second dielectric layer between the adjacent capacitors.

公开(公告)号：US11522060B2

公开(公告)日：2022-12-06

申请号：US16142036

申请日：2018-09-26

Applicant: Intel Corporation

Inventor： Seung Hoon Sung ,  Justin Weber ,  Matthew Metz ,  Arnab Sen Gupta ,  Abhishek Sharma ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Charles Kuo ,  Nazila Haratipour ,  Shriram Shivaraman ,  Van H. Le ,  Tahir Ghani ,  Jack T. Kavalieros ,  Sean Ma

IPC: H01L29/417 ,  H01L29/08 ,  H01L29/205 ,  H01L29/49 ,  H01L29/786 ,  H01L29/45 ,  H01L27/108 ,  H01L21/02 ,  H01L29/267 ,  H01L29/66

Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT) above a substrate. The transistor includes a contact electrode having a conductive material above the substrate, an epitaxial layer above the contact electrode, and a channel layer including a channel material above the epitaxial layer and above the contact electrode. The channel layer is in contact at least partially with the epitaxial layer. A conduction band of the channel material and a conduction band of a material of the epitaxial layer are substantially aligned with an energy level of the conductive material of the contact electrode. A bandgap of the material of the epitaxial layer is smaller than a bandgap of the channel material. Furthermore, a gate electrode is above the channel layer, and separated from the channel layer by a gate dielectric layer. Other embodiments may be described and/or claimed.

公开(公告)号：US11522012B2

公开(公告)日：2022-12-06

申请号：US16147091

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Jack T. Kavalieros ,  Ian A. Young ,  Ram Krishnamurthy ,  Ravi Pillarisetty ,  Sasikanth Manipatruni ,  Gregory Chen ,  Hui Jae Yoo ,  Van H. Le ,  Abhishek Sharma ,  Raghavan Kumar ,  Huichu Liu ,  Phil Knag ,  Huseyin Sumbul

IPC: H01L27/24 ,  G11C13/00 ,  H01L45/00 ,  H01L29/51

Abstract: A DIMA semiconductor structure is disclosed. The DIMA semiconductor structure includes a frontend including a semiconductor substrate, a transistor switch of a memory cell coupled to the semiconductor substrate and a computation circuit on the periphery of the frontend coupled to the semiconductor substrate. Additionally, the DIMA includes a backend that includes an RRAM component of the memory cell that is coupled to the transistor switch.

公开(公告)号：US11502696B2

公开(公告)日：2022-11-15

申请号：US16160800

申请日：2018-10-15

Applicant: Intel Corporation

Inventor： Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor Lee ,  Huseyin Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  Ian Young ,  Abhishek Sharma

IPC: H03M1/00 ,  H03M1/12 ,  G06N3/063 ,  G06N3/04 ,  G06N3/08

Abstract: Embodiments are directed to systems and methods of implementing an analog neural network using a pipelined SRAM architecture (“PISA”) circuitry disposed in on-chip processor memory circuitry. The on-chip processor memory circuitry may include processor last level cache (LLC) circuitry. One or more physical parameters, such as a stored charge or voltage, may be used to permit the generation of an in-memory analog output using a SRAM array. The generation of an in-memory analog output using only word-line and bit-line capabilities beneficially increases the computational density of the PISA circuit without increasing power requirements. Thus, the systems and methods described herein beneficially leverage the existing capabilities of on-chip SRAM processor memory circuitry to perform a relatively large number of analog vector/tensor calculations associated with execution of a neural network, such as a recurrent neural network, without burdening the processor circuitry and without significant impact to the processor power requirements.

公开(公告)号：US11482622B2

公开(公告)日：2022-10-25

申请号：US16214706

申请日：2018-12-10

Applicant: INTEL CORPORATION

Inventor： Kevin Lin ,  Abhishek Sharma ,  Carl Naylor ,  Urusa Alaan ,  Christopher Jezewski ,  Ashish Agrawal

IPC: H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/768 ,  H01L29/24 ,  H01L29/417

Abstract: A transistor structure includes a layer of active material on a base. The base can be insulator material in some cases. The layer has a channel region between a source region and a drain region. A gate structure is in contact with the channel region and includes a gate electrode and a gate dielectric, where the gate dielectric is between the gate electrode and the active material. An electrical contact is on one or both of the source region and the drain region. The electrical contact has a larger portion in contact with a top surface of the active material and a smaller portion extending through the layer of active material into the base. The active material may be, for example, a transition metal dichalcogenide (TMD) in some embodiments.

公开(公告)号：US11476366B2

公开(公告)日：2022-10-18

申请号：US15943584

申请日：2018-04-02

Applicant: Intel Corporation

Inventor： Sean Ma ,  Abhishek Sharma ,  Gilbert Dewey ,  Jack T. Kavalieros ,  Van H. Le

IPC: H01L29/786 ,  H01L29/417 ,  H01L29/49 ,  H01L27/12 ,  H01L29/78

Abstract: A transistor is described. The transistor includes a substrate, a first semiconductor structure above the substrate, a second semiconductor structure above the substrate, a source contact that includes a first metal structure that contacts a plurality of surfaces of the first semiconductor structure and a drain contact that includes a second metal structure that contacts a plurality of surfaces of the second semiconductor structure. The transistor also includes a gate below a back side of the substrate.

公开(公告)号：US11450750B2

公开(公告)日：2022-09-20

申请号：US16146654

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Nazila Haratipour ,  Tahir Ghani ,  Jack T. Kavalieros ,  Gilbert Dewey ,  Benjamin Chu-Kung ,  Seung Hoon Sung ,  Van H. Le ,  Shriram Shivaraman ,  Abhishek Sharma

IPC: H01L23/532 ,  H01L29/51 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423 ,  H01L29/417 ,  H01L27/10 ,  H01L27/105

Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT). The transistor includes a source electrode oriented in a horizontal direction, and a channel layer in contact with a portion of the source electrode and oriented in a vertical direction substantially orthogonal to the horizontal direction. A gate dielectric layer conformingly covers a top surface of the source electrode and surfaces of the channel layer. A gate electrode conformingly covers a portion of the gate dielectric layer. A drain electrode is above the channel layer, oriented in the horizontal direction. A current path is to include a current portion from the source electrode along a gated region of the channel layer under the gate electrode in the vertical direction, and a current portion along an ungated region of the channel layer in the horizontal direction from the gate electrode to the drain electrode. Other embodiments may be described and/or claimed.