公开(公告)号：WO1998015115A1

公开(公告)日：1998-04-09

申请号：PCT/US1997015221

申请日：1997-08-27

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  TREVINO, Roy

IPC: H04N03/14

CPC classification number: H04N5/3532 ,  H04N5/374

Abstract: An apparatus for controlling a CMOS sensor array (2) containing a first CMOS sensor cell (cell 0), including a first logic circuit (30) for receiving a clock signal (clock) and generating a first address; a second logic circuit (36) coupled to the first logic circuit for receiving the first address and generating a reset signal to the first CMOS sensor cell based on the first address; a third logic circuit (34) coupled to the first logic circuit for receiving the first address and calculating a read delay based on the first address and an offset value; and a fourth logic circuit (32) coupled to the first logic circuit for generating a read address signal to the first CMOS sensor cell after the read delay.

Abstract translation: 一种用于控制包含第一CMOS传感器单元（单元0）的CMOS传感器阵列（2）的装置，包括用于接收时钟信号（时钟）并产生第一地址的第一逻辑电路（30） 第二逻辑电路（36），耦合到所述第一逻辑电路，用于接收所述第一地址，并基于所述第一地址向所述第一CMOS传感器单元产生复位信号; 耦合到第一逻辑电路的第三逻辑电路（34），用于接收第一地址并基于第一地址和偏移值计算读延迟; 以及耦合到第一逻辑电路的第四逻辑电路（32），用于在读取延迟之后产生到第一CMOS传感器单元的读取地址信号。

公开(公告)号：WO1998014875A1

公开(公告)日：1998-04-09

申请号：PCT/US1997012994

申请日：1997-07-23

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  DERR, Michael, N.

IPC: G06F12/00

CPC classification number: G06F13/28

Abstract: A method and apparatus for performing a system memory read initiated by a bus master (150). In the prior art, a memory controller (140) monitored activity on a system memory bus (180) to determine whether to close a page of memory. Therefore, if a stall occurred during a burst read, the system memory bus (180) would be idle and the page of system memory (130) would be closed. The present invention keeps the page of system memory (130) open during the entire burst read, even if the system memory bus (180) becomes idle. Thus, latencies involved in opening and closing the page of system memory (130) can be avoided. The present invention opens a page of system memory (130) when receiving a first command, and is closed when a second command indicating the termination of the read operation is received from the bus master (150).

Abstract translation: 一种用于执行由总线主机（150）发起的系统存储器读取的方法和装置。 在现有技术中，存储器控制器（140）监视系统存储器总线（180）上的活动以确定是否关闭存储器页面。 因此，如果在突发读取期间发生停顿，则系统存储器总线（180）将是空闲的，并且系统存储器（130）的页面将被关闭。 即使系统存储器总线（180）变空闲，本发明在整个突发读取期间保持系统存储器（130）的页面打开。 因此，可以避免涉及打开和关闭系统存储器（130）的页面的延迟。 本发明在接收到第一命令时打开系统存储器页面（130），并且当从总线主机（150）接收到指示读取操作的终止的第二命令时，该程序段被关闭。

公开(公告)号：WO1998010630A1

公开(公告)日：1998-03-12

申请号：PCT/US1997011277

申请日：1997-06-27

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  BANERJEE, Koushik ,  CHRONEOS, Robert, J., Jr. ,  MOZDZEN, Tom

IPC: H05K07/20

CPC classification number: H01L23/642 ,  H01L23/13 ,  H01L23/49827 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/49109 ,  H01L2224/85444 ,  H01L2924/00014 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: An integrated circuit package (10). The package includes a substrate (12) that has a first internal conductive bus (72) and a second internal conductive bus (74) that are located on a common layer of the substrate and dedicated to different power voltage levels. The busses are coupled to external lands located on a first surface (14) of the package by vias (32) that extend through the substrate. The first and second busses are located on a common layer of the substrate. The package contains an integrated circuit (18) which is mounted to a heat slug (22) that is attached to a second surface of the package. The integrated circuit is coupled to bond fingers located on a shelf of the substrate. Some of the bond fingers (40) are connected to the internal busses by conductive strips (68) that wrap around the edges of the shelf. Some of the vias are connected to a whole group of external lands. Grouping the lands (34g) to a single via reduces the number of vias on the second surface of the package. The reduction in vias allows additional capacitors (28) to be mounted to the second surface of the package.

Abstract translation: 集成电路封装（10）。 封装包括具有位于衬底的公共层上并专用于不同功率电压电平的第一内部导电总线（72）和第二内部导电总线（74）的衬底（12）。 总线通过延伸穿过衬底的通孔（32）耦合到位于封装的第一表面（14）上的外部焊盘。 第一和第二总线位于基板的公共层上。 该封装包含集成电路（18），该集成电路安装到附接到封装的第二表面上的散热块（22）。 集成电路耦合到位于基板的架子上的键指。 一些接合指状物（40）通过围绕搁板边缘的导电条（68）连接到内部总线上。 一些通道连接到一整套外部土地。 将焊盘（34g）分组到单个通孔减少了封装的第二表面上的通孔数量。 通孔的减小允许将额外的电容器（28）安装到封装的第二表面。

公开(公告)号：WO1998009221A1

公开(公告)日：1998-03-05

申请号：PCT/US1997011632

申请日：1997-07-01

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  McWILLIAMS, Peter, D. ,  PAWLOWSKI, Stephen, S.

IPC: G06F12/02

CPC classification number: G06F11/1016 ,  G06F12/0623

Abstract: A method and apparatus for supporting multiple overlapping address spaces on a shared bus (401) includes both an address comparator (420) and an address size indicator (435). The address comparator (420) compares an address, corresponding to a request to be issued on the bus (401), to a plurality of address spaces. The address size indicator (435) indicates a first address space of the plurality of address spaces to which the address corresponds.

Abstract translation: 在共享总线（401）上支持多个重叠地址空间的方法和装置包括地址比较器（420）和地址大小指示器（435）。 地址比较器（420）将对应于要在总线（401）上发出的请求的地址与多个地址空间进行比较。 地址大小指示符（435）表示地址对应的多个地址空间的第一地址空间。

公开(公告)号：WO1997050205A1

公开(公告)日：1997-12-31

申请号：PCT/US1997010292

申请日：1997-06-11

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  DAVIS, Derek, L.

IPC: H04K01/00

CPC classification number: H04L9/3263 ,  G06Q20/3674 ,  G06Q20/401 ,  G06Q40/04 ,  H04L9/3247 ,  H04L63/123

Abstract: A digital arbitration system comprising a server node and at least one signatory node (310) coupled together through a communication link (315). Each of the signatory node(s) may be configured to include a unique private key which is used to digitally sign a message, a hash value of an electronic document for example, and transmits the digitally signed message, being a digital signature, to the server node via the communication link. The server node (fig. 7) determines whether the digital signatures have been received from at least one the signatory node(s) and whether each of the digital signatures is valid. The server node then transmits all of the digital signatures to each of the signatory node(s), provided both conditions described have been met.

Abstract translation: 一种数字仲裁系统，包括通过通信链路（315）耦合在一起的服务器节点和至少一个签名节点（310）。 每个签署者节点可以被配置为包括用于对消息进行数字签名的唯一专用密钥，例如电子文档的哈希值，并将作为数字签名的数字签名的消息发送到 服务器节点通过通信链路。 服务器节点（图7）确定是否已经从至少一个签署者节点接收到数字签名以及每个数字签名是否有效。 服务器节点然后将所有数字签名发送给每个签署者节点，只要已经满足描述的两个条件。

公开(公告)号：WO1997050031A1

公开(公告)日：1997-12-31

申请号：PCT/US1997010341

申请日：1997-06-17

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  FARBER, Yaron ,  LEVHARI, Yossi ,  BARAZ, Leonid ,  LADIRAY, Gallia

IPC: G06F09/455

CPC classification number: G06F9/30174 ,  G06F8/443 ,  G06F9/30094 ,  G06F9/3808

Abstract: A method for increasing the performance of binary translated conditional instructions (162). According to one embodiment of the invention, a conditional instruction compatible with the first ISA is decoded (BB1). The condition of the conditional instruction is dependent on at least one status flag (ZF=1). The conditional instruction is translated to be compatible with a second ISA (144), wherein the condition of the conditional instructions is altered to be dependent on a previously computed difference between two values (162), the difference residing in a memory location (REG3).

Abstract translation: 一种用于增加二进制翻译条件指令（162）的性能的方法。 根据本发明的一个实施例，解码与第一ISA兼容的条件指令（BB1）。 条件指令的条件取决于至少一个状态标志（ZF = 1）。 条件指令被转换为与第二ISA（144）兼容，其中条件指令的条件被改变为依赖于先前计算的两个值（162）之间的差异，驻留在存储器位置（REG3）中的差异 。

公开(公告)号：WO1997049041A1

公开(公告)日：1997-12-24

申请号：PCT/US1997008946

申请日：1997-05-22

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  POISNER, David, I.

IPC: G06F15/00

CPC classification number: G06F9/3869

Abstract: A method of providing access to an input/output (I/O) mapped register (60) of a computer system (18) is described. The computer system (18) includes a processor (20) operable in a system management mode (SMM), in which the processor (20) accesses a dedicated system management memory space, a real mode, a protected mode and a virtual 8086 mode. The method includes the steps of firstly receiving an access request at the I/O mapped register (60). Logic circuitry (64) associated with the I/O mapped register (60) then determines whether the processor (20) is operating in SMM by examining the status of a system management interrupt acknowledge (SMIACT#) output of the processor (20). If the logic circuitry (64) determines that the processor (20) is operating in SMM, a first, unrestricted type of access by the processor (20) to the I/O mapped register (60) is provided. Alternatively, if the logic circuitry (64) determines that the processor (20) is not operating in SMM, a second, restricted type of access by the processor (20) to the I/O mapped register (60) is provided. If the first, unrestricted type of access is provided to the processor (20), it performs an operation, under the direction of code stored in the dedicated system management memory address space, on the contents of the I/O mapped register (60).

Abstract translation: 描述了提供对计算机系统（18）的输入/输出（I / O）映射寄存器（60）的访问的方法。 计算机系统（18）包括以系统管理模式（SMM）操作的处理器（20），其中处理器（20）访问专用系统管理存储器空间，实模式，保护模式和虚拟8086模式。 该方法包括首先在I / O映射寄存器（60）处接收访问请求的步骤。 与I / O映射寄存器（60）相关联的逻辑电路（64）然后通过检查处理器（20）的系统管理中断确认（SMIACT＃）输出的状态来确定处理器（20）是否在SMM中操作。 如果逻辑电路（64）确定处理器（20）在SMM中操作，则提供由处理器（20）到I / O映射寄存器（60）的第一无限制类型的访问。 或者，如果逻辑电路（64）确定处理器（20）不在SMM中操作，则提供处理器（20）到I / O映射寄存器（60）的第二限制类型的访问。 如果向处理器（20）提供第一种不受限制的访问类型，则在存储在专用系统管理存储器地址空间中的代码的方向上执行对I / O映射寄存器（60）的内容的操作， 。

公开(公告)号：WO1997047135A1

公开(公告)日：1997-12-11

申请号：PCT/US1997009178

申请日：1997-06-04

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  WILLIAMS, Christopher, D. ,  GOLDSCHMIDT IKI, Jean, M. ,  SHAH-NAZAROFF, Anthony, A. ,  WATTS, Earl, Michael ,  HACKSON, David, N. ,  MOORE, Kenneth, A.

IPC: H04N07/00

CPC classification number: H04H60/46 ,  G11B27/105 ,  G11B27/11 ,  H04N5/44 ,  H04N7/10 ,  H04N7/17354 ,  H04N17/04 ,  H04N21/441 ,  H04N21/44222 ,  H04N21/4532 ,  H04N21/454 ,  H04N21/4622 ,  H04N21/466 ,  H04N21/4667 ,  H04N21/812

Abstract: A method and apparatus for automatically determining and dynamically updating user preferences in an entertainment system is provided. In a first embodiment, an apparatus comprises a storage medium (616) to store user preference information corresponding to at least a subset of a plurality of entertainment system users and a processor agent (604). The processor agent (604), communicatively coupled to the storage medium, is operative to monitor user interaction with the entertainment system and to automatically detect which user of the plurality of entertainment system users is currently using the entertainment system.

Abstract translation: 提供一种用于在娱乐系统中自动确定和动态更新用户偏好的方法和装置。 在第一实施例中，一种装置包括存储介质（616），用于存储对应于多个娱乐系统用户的至少一个子集的用户偏好信息和处理器代理（604）。 通信地耦合到存储介质的处理器代理（604）可操作以监视与娱乐系统的用户交互并自动检测多个娱乐系统用户当前正在使用娱乐系统的用户。

公开(公告)号：WO1997046068A1

公开(公告)日：1997-12-04

申请号：PCT/US1997007788

申请日：1997-05-06

Applicant: INTEL CORPORATION ,  O'CONNOR, Michael ,  HALEY, Kevin ,  BHATIA, Rakesh ,  ADAMS, Daniel, Thomas ,  KAST, Michael, Andrew

Inventor： INTEL CORPORATION

IPC: H05K07/20

CPC classification number: G06F1/203

Abstract: An apparatus and method for removing heat from a heat generating component located within a thin profile consumer electronic or computer system enclosure is disclosed. In one embodiment, the cooling system of the present invention includes an air duct comprising a thermally conductive housing (10) having internal fins dispersed along the internal walls of the duct. An air flow generator (16) produces an air flow that is directed from an inlet port (13) located at or near the center of the air duct to first and second exit ports (18, 20) located at opposite ends of the duct. A low resistance thermal path, such as a heat pipe, transfers heat from the heat generating component to the air duct housing.

Abstract translation: 公开了一种用于从位于薄型消费电子或计算机系统外壳内的发热部件移除热量的装置和方法。 在一个实施例中，本发明的冷却系统包括一个空气管道，它包括一个导热壳体（10），该导热壳体具有沿导管内壁分散的内部散热片。 气流发生器（16）产生从位于空气管道中心或附近的入口（13）引导到位于管道相对端的第一和第二出口（18,20）的空气流。 诸如热管的低电阻热路径将热量从发热部件传递到风管壳体。

公开(公告)号：WO1997046067A1

公开(公告)日：1997-12-04

申请号：PCT/US1996018075

申请日：1996-11-14

Applicant: INTEL CORPORATION ,  O'CONNOR, Michael ,  HALEY, Kevin ,  BHATIA, Rakesh ,  ADAMS, Daniel, T. ,  KAST, Michael, A.

Inventor： INTEL CORPORATION

IPC: H05K07/20

CPC classification number: G06F1/203

Abstract: An apparatus and method for removing heat from a heat generating component located within a thin-profile consumer electronic or computer system enclosure (120) is disclosed. In one embodiment the cooling system of the present invention includes an air duct (11) comprising a thermally conductive housing (12, 14) having internal fins (50, 52) dispersed along the internal walls of the duct. An air flow generator (16) produces an air flow that is directed from an inlet port (13) located at or near the center of the air duct to first and second exit ports (18, 20) located at opposite ends of the duct. A low resistance thermal path, such as a heat pipe, transfers heat from the heat generating component (80) to the air duct housing.

Abstract translation: 公开了一种用于从位于薄型消费电子或计算机系统外壳（120）内的发热部件移除热量的装置和方法。 在一个实施例中，本发明的冷却系统包括一个包括导热壳体（12,14）的空气管道（11），该导热壳体具有沿导管内壁分散的内部翅片（50,52）。 气流发生器（16）产生从位于空气管道中心或附近的入口（13）引导到位于管道相对端的第一和第二出口（18,20）的空气流。 诸如热管的低电阻热路径将热量从发热部件（80）传递到风管壳体。