公开(公告)号：WO1999034270A1

公开(公告)日：1999-07-08

申请号：PCT/US1997024026

申请日：1997-12-29

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  MASSIE, Harold, L.

IPC: G05F03/02

CPC classification number: H02H3/243 ,  Y10T307/735

Abstract: A transient suppression circuit suppresses transients on a dc power bus (15), extending between a power supply (11) and a load (14) which carries a first voltage having a nominal value, by charging a capacitor (33) to a second voltage greater than the nominal voltage, detecting a threshold at which the first voltage drops below its nominal value by more than a first predetermined amount and coupling energy from the capacitor to the bus (15) to compensate for the drop in voltage in response to detecting the threshold.

Abstract translation: 瞬态抑制电路通过将电容器（33）充电到第二电压来抑制在电源（11）和承载具有标称值的第一电压的负载（14）之间延伸的直流电源总线（15）上的瞬变 大于标称电压，检测第一电压低于其标称值超过第一预定量的阈值，并将来自电容器的能量耦合到总线（15），以补偿响应于检测到的电压的下降 阈。

公开(公告)号：WO1998032063A2

公开(公告)日：1998-07-23

申请号：PCT/US1997022147

申请日：1997-12-03

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  JAYAKUMAR, Muthurajan ,  HUANG, Sunny, C. ,  MACWILLIAMS, Peter, D. ,  WU, William, S. ,  PAWLOWSKI, Stephen ,  PRASAD, Bindi, A.

IPC: G06F00/00

CPC classification number: G06F13/37 ,  G06F13/4252

Abstract: A split transaction bus in a computer system that permits out-of-order replies in a pipelined manner using an additional bus for use in the response phase.

Abstract translation: 计算机系统中的分流事务总线，其允许使用附加总线以流水线方式进行无序回复以用于响应阶段。

公开(公告)号：WO1998029949A1

公开(公告)日：1998-07-09

申请号：PCT/US1997023372

申请日：1997-12-17

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  FLETCHER, Thomas, D.

IPC: H03K19/00

CPC classification number: H03K19/0963

Abstract: A domino logic circuit configuration including self-timed resets (752), a pulsed clock input terminal in a first stage (712), a self-terminating pulsed clock precharge circuit in a second stage (730) which also has a pulsed clock input terminal, and a full-keeper (734, 736) in the second stage, provides time borrowing capability and reduced sensitivity to clock jitter in high frequency designs. In an embodiment, both the evaluate of the first domino stage (718) of a block and the self-terminating precharge of the last domino stage (746) of the block are initiated by the rising edge of a pulsed clock (702). In a circuit configuration in accordance with the present invention, a time period approximately equivalent to three inverter delays is provided to turn off the inputs to a subsequent domino logic stage, thus providing adequate time to evaluate the first domino logic stage in each block.

Abstract translation: 包括自定时复位（752），第一级中的脉冲时钟输入端（712），第二级（730）中的自终止脉冲时钟预充电电路的多米诺逻辑电路配置，其还具有脉冲时钟输入端 ，以及第二阶段的全员（734,736），提供了时间借用能力，降低了高频设计中时钟抖动的灵敏度。 在一个实施例中，块的第一多米诺舞台（718）的评估和块的最后多米诺舞台（746）的自终止预充电由脉冲时钟（702）的上升沿启动。 在根据本发明的电路配置中，提供了大约相当于三个逆变器延迟的时间段，以将输入关断到随后的多米诺逻辑级，从而提供足够的时间来评估每个块中的第一多米诺逻辑级。

公开(公告)号：WO1998029816A1

公开(公告)日：1998-07-09

申请号：PCT/US1997018425

申请日：1997-10-14

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  PASHLEY, Richard, D. ,  WINSTON, Mark, D. ,  JUNGROTH, Owen, W. ,  KAPLAN, David, J.

IPC: G06F13/00

CPC classification number: G11C11/005

Abstract: An integrated circuit (IC) memory device (100) and method for interfacing volatile and non volatile memory arrays formed on a single semiconductor substrate. Data to be written from an external device such as a processor (104) is initially written to a volatile random access memory (RAM) write buffer array (101), and then written from the volatile RAM array (101) to a nonvolatile flash array (103) via an interface (102) to provide nonvolatile data storage at speeds typical of a RAM device. Data from first and second block addresses in the arrays may be merged in a flash merge buffer, and validity bits may be used to ensure data coherency. Data may be simultaneously written to or read from the volatile RAM array (101) during a time in which data is being read from or written to the nonvolatile flash array (103), which may be an EPROM or EEPROM.

Abstract translation: 一种集成电路（IC）存储器件（100）以及用于对形成在单个半导体衬底上的易失性和非易失性存储器阵列进行接口的方法。 要从诸如处理器（104）的外部设备写入的数据被初始写入到易失性随机存取存储器（RAM）写入缓冲器阵列（101）中，然后从易失性RAM阵列（101）写入非易失性闪存阵列 （103）经由接口（102），以在RAM设备的典型速度下提供非易失性数据存储。 阵列中的第一和第二块地址的数据可以合并在闪存合并缓冲器中，并且可以使用有效位来确保数据一致性。 在数据被读取或写入非易失性闪存阵列（103）的时间期间，数据可以被同时写入到易失性RAM阵列（101）或从易失性RAM阵列读取，所述非易失性闪存阵列（103）可以是EPROM或EEPROM。

公开(公告)号：WO1998028914A1

公开(公告)日：1998-07-02

申请号：PCT/US1997023391

申请日：1997-12-16

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  CAHILL, Benjamin, M., III.

IPC: H04N07/087

CPC classification number: H04N7/0352 ,  H04N7/035

Abstract: A method and apparatus for supporting variable oversampling ratios when decoding vertical blanking interval data receives an indication of an oversampling ratio (205) being used to sample a signal received during the vertical blanking interval. The sampled signal is also received. Then, based on the indication of the oversampling ratio being used, the data embedded in the vertical blanking period is identified (225).

Abstract translation: 解码垂直消隐间隔数据时用于支持可变过采样比的方法和装置接收用于采样在垂直消隐间隔期间接收到的信号的过采样比（205）的指示。 也接收采样信号。 然后，基于所使用的过采样比的指示，识别嵌入垂直消隐期的数据（225）。

公开(公告)号：WO1998027492A1

公开(公告)日：1998-06-25

申请号：PCT/US1997022659

申请日：1997-12-12

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  MITTAL, Millind

IPC: G06F12/08

CPC classification number: G06F9/30047 ,  G06F12/0888 ,  G06F12/0897

Abstract: A computer system and method in which allocation of a cache memory (21a, 22a) is managed by utilizing a locality hint value (17, 18), included within an instruction (19), which controls if cache allocation is to be made. The locality value is based on spatial and/or temporal locality for a data access and may be assigned to each level of a cache hierarchy where allocation control is desired. The locality hint value may be used to identify a lowest level where management of cache allocation is desired and cache is allocated at that level and any higher level or levels. If the locality hint identifies a particular access for data as temporal or non-temporal with respect to a particular cache level, the particular access may be determined to be temporal or non-temporal with respect to the higher and lower cache levels.

Abstract translation: 一种计算机系统和方法，其中通过利用包括在控制是否要进行高速缓存分配的指令（19）内的位置提示值（17,18）来管理高速缓冲存储器（21a，22a）的分配。 位置值基于用于数据访问的空间和/或时间局部性，并且可以被分配给期望分配控制的高速缓存层级的每个级别。 可以使用本地提示值来识别希望管理高速缓存分配的最低级别，并且在该级别和任何更高级别或级别上分配高速缓存。 如果局部性提示将数据的特定访问识别为相对于特定高速缓存级别的时间或非时间，则可以将特定访问确定为相对于较高和较低高速缓存级别的时间或非时间。

公开(公告)号：WO1998026576A2

公开(公告)日：1998-06-18

申请号：PCT/US1997022038

申请日：1997-12-09

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  DANG, Nam, V. ,  ADAMS, Lewis, E., III

IPC: H04N00/00

CPC classification number: H04N5/4446 ,  H03D7/163 ,  H04N7/102 ,  H04N7/16

Abstract: A method of tuning channels for television and community antenna television (CATV) devices includes the step of receiving a radio frequency input (RFI) signal having at least one carrier signal at frequency fS associated with a selected broadcast channel. The RFI signal is up-converted by m to a first intermediate frequency wherein the carrier signal is located at fS + m. The first intermediate frequency is filtered. The filtered first intermediate frequency is down-converted by n to a second intermediate frequency wherein the second intermediate frequency includes the carrier signal at fS + m - n. Additional methods for improving the reception of the selected channel include the step of varying m and n in order to avoid frequency-dependent anomalies within the pass band of the filter. For digital communications, m and n are varied in accordance with an error rate of the digital communications in order to reduce the error rate of the digital communications.

Abstract translation: 用于电视和社区天线电视（CATV）设备的调谐频道的方法包括接收具有与选择的广播频道相关联的频率fS的至少一个载波信号的射频输入（RFI）信号的步骤。 RFI信号由m上变频到第一中频，其中载波信号位于fS + m。 第一个中频被过滤。 滤波后的第一中频由n下变频到第二中频，其中第二中频包括fS + m-n处的载波信号。 用于改善所选信道的接收的附加方法包括改变m和n的步骤，以避免滤波器的通带内的频率相关异常。 对于数字通信，m和n根据数字通信的错误率而变化，以便减少数字通信的错误率。

公开(公告)号：WO1998022968A1

公开(公告)日：1998-05-28

申请号：PCT/US1997017491

申请日：1997-09-29

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  CHO, Sung-Soo ,  BRYANT, Diane, M. ,  KARDACH, James, P. ,  DENG, Feng

IPC: H01J03/00

CPC classification number: G06F13/4081 ,  G06F1/1632 ,  Y02D10/14 ,  Y02D10/151

Abstract: Prior art quiet docking and undocking method used an interface that was located within notebook computer (10), thus adding to the cost, complexity, weight, and power consumption of the notebook computer (10). The present invention provides for an apparatus for quiet docking of a notebook computer (10) to a docking station (11), including interface circuitry located within the docking station. The interface detects when the notebook computer (10) has been inserted within the docking station (11), and correspondingly enables a switch such that a common system bus is coupled between the notebook computer (10) and docking station (11). The interface also generates events to allow a software routine to configure the notebook computer (10) and docking station (11) without prior user intervention. The interface also includes cicuitry to detect an undock request, and correspondingly undock the computer such that a transaction occurring on the system bus is not affected.

Abstract translation: 现有技术的安静对接和脱离方法使用位于笔记本计算机（10）内的接口，从而增加笔记本计算机（10）的成本，复杂性，重量和功率消耗。 本发明提供了一种用于将笔记本计算机（10）安静地对接到对接站（11）的装置，包括位于对接站内的接口电路。 接口检测笔记本电脑（10）何时插入对接站（11）内，并且相应地启用开关，使得公共系统总线耦合在笔记本计算机（10）和坞站（11）之间。 界面还生成事件，以允许软件程序配置笔记本电脑（10）和扩展坞（11），无需用户干预。 该接口还包括检测未停靠请求的缓存，并相应地将计算机取消停靠，使得系统总线上发生的事务不受影响。

公开(公告)号：WO1998020414A1

公开(公告)日：1998-05-14

申请号：PCT/US1997013504

申请日：1997-07-30

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  MEYER, Paul, G. ,  STRAZDUS, Stephen ,  O'CONNOR, Dennis ,  ADELMEYER, Thomas ,  HEEB, Jay ,  TOPPS, Avery

IPC: G06F09/30

CPC classification number: G06F9/3802 ,  G06F9/3867

Abstract: A processor core suitable for use with a wide variety of instruction fetch units. The processor core contains a plurality of pipe stages including an instruction pointer generation stage (52) and a decoding stage (55). The core bundles all control necessary for downstream pipeline operation with an instruction address in a first stage. The bundle is transmitted outside the core to the instruction fetch unit (59). The instruction fetch unit (59) fetches the instruction and adds it to the bundle, before forwarding the bundle as modified back within the core and down the pipeline. In this way, an external pipeline is introduced providing a connection between discontinuous pipe stages in the core. Additionally, by bundling the control signals and address information in a single bundle that traverses the external pipe stage as a group, synchronization concerns are reduced or eliminated.

Abstract translation: 适用于各种指令提取单元的处理器核心。 处理器核心包括多个管级，包括指令指针产生级（52）和解码级（55）。 核心将下游管道运行所需的所有控制与第一阶段的指令地址进行捆绑。 捆绑包在核心外部传送到指令提取单元（59）。 指令获取单元（59）获取指令并将其添加到捆绑包中，然后在核心内向下流出管道之前转发捆绑包。 以这种方式，引入外部管道，提供核心中的不连续管段之间的连接。 此外，通过将跨越外部管道级的单个束中的控制信号和地址信息捆绑为一组，减少或消除了同步问题。

公开(公告)号：WO1998019241A1

公开(公告)日：1998-05-07

申请号：PCT/US1997013918

申请日：1997-08-06

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  LEEMANN, Daniel, H.

IPC: G06F11/10

CPC classification number: G06F11/1072 ,  G11C11/56 ,  G11C11/5621 ,  G11C11/5642 ,  G11C29/00

Abstract: A method and apparatus corrects data read from a multilevel cell memory (204). The multilevel cell is capable of storing three or more charge states. A first charge state read from the multilevel cell is determined to be erroneous. An output is provided corresponding to that which would be provided if the multilevel cell were maintaining a second state, wherein the second charge state has more charge than the first state.

Abstract translation: 方法和装置校正从多级单元存储器（204）读取的数据。 多电平单元能够存储三个或更多的充电状态。 从多电平单元读取的第一充电状态被确定为错误的。 如果多电平单元保持第二状态，则提供相应的输出，其中第二充电状态具有比第一状态更多的电荷。