公开(公告)号：US10929134B2

公开(公告)日：2021-02-23

申请号：US16457238

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Radhakrishna Sripada ,  Peter Yiannacouras ,  Josh Triplett ,  Nagabhushan Chitlur ,  Kalyan Kondapally

IPC: G06T1/20 ,  G06F9/30

Abstract: A processor to facilitate acceleration of instruction execution is disclosed. The processor includes a plurality of execution units (EUs), each including an instruction decode unit to decode an instruction into one or more operands and opcode defining an operation to be performed at an accelerator, a register file having a plurality of registers to store the one or more operands and an accelerator having programmable hardware to retrieve the one or more operands from the register file and perform the operation on the one or more operands.

公开(公告)号：US10860709B2

公开(公告)日：2020-12-08

申请号：US16024547

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Michael Lemay ,  David M. Durham ,  Michael E. Kounavis ,  Barry E. Huntley ,  Vedvyas Shanbhogue ,  Jason W. Brandt ,  Josh Triplett ,  Gilbert Neiger ,  Karanvir Grewal ,  Baiju V. Patel ,  Ye Zhuang ,  Jr-Shian Tsai ,  Vadim Sukhomlinov ,  Ravi Sahita ,  Mingwei Zhang ,  James C. Farwell ,  Amitabh Das ,  Krishna Bhuyan

IPC: G06F21/53 ,  G06F12/02

Abstract: Disclosed embodiments relate to encoded inline capabilities. In one example, a system includes a trusted execution environment (TEE) to partition an address space within a memory into a plurality of compartments each associated with code to execute a function, the TEE further to assign a message object in a heap to each compartment, receive a request from a first compartment to send a message block to a specified destination compartment, respond to the request by authenticating the request, generating a corresponding encoded capability, conveying the encoded capability to the destination compartment, and scheduling the destination compartment to respond to the request, and subsequently, respond to a check capability request from the destination compartment by checking the encoded capability and, when the check passes, providing a memory address to access the message block, and, otherwise, generating a fault, wherein each compartment is isolated from other compartments.

公开(公告)号：US10534935B2

公开(公告)日：2020-01-14

申请号：US15200935

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Jose S. Niell ,  Gautham N. Chinya ,  Khee Wooi Lee ,  William A. Stevens, Jr. ,  Josh Triplett

IPC: G06F21/70

Abstract: A system-on-chip (SoC) includes a host CPU on a CPU fabric, the host CPU including multiple processor cores, each associated with multiple security attributes. The SoC includes a secure asset on a network-on-chip and a security co-processor. The security co-processor includes circuitry to detect requests from the processor cores targeting the secure asset and security function processing requests, to determine, based on associated security attributes, whether the core or function is authorized to access the secure asset, to allow the request to be issued, if the core or function is so authorized, and to prevent its issuance, if not. The determination may be dependent on a signal from the CPU fabric indicating whether the host CPU can modify its security attributes or they are locked down. The security co-processor may have the highest security level and may be the only master on the SoC that can access the secure asset.

公开(公告)号：US20190034928A1

公开(公告)日：2019-01-31

申请号：US15812614

申请日：2017-11-14

Applicant: Intel Corporation

Inventor： Josh Triplett ,  Philip Hanson ,  Justin Moore

IPC: G06Q20/40 ,  G06F9/54 ,  G06Q20/12 ,  G06Q20/34

Abstract: Methods, apparatus, systems and articles of manufacture to securely handle chip card data are disclosed. An example method includes providing, by executing an instruction with a first processor of a client device, an application programming interface (API) in a web client of the client device, in response to detecting, in the web client at the client device, a query from a server for card data, operating, by executing an instruction with the first processor of the client device, the API in the web client at the client device to obtain the card data stored on a chip of a chip card communicatively coupled to the client device, and sending, by executing an instruction with the first processor of the client device, the card data to the server.