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    Apparatus and method for pausing processor trace for efficient analysis
    11.
    发明授权
    Apparatus and method for pausing processor trace for efficient analysis 有权

    公开(公告)号：US11360876B2

    公开(公告)日：2022-06-14

    申请号：US16845512

    申请日：2020-04-10

    Applicant: Intel Corporation

    Inventor： Michael Lemay ,  Beeman Strong

    IPC: G06F11/34 ,  G06F11/30 ,  G06F21/57 ,  G06F21/56

    Abstract: Processor trace systems and methods are described. For example, one embodiment comprises executing instrumented code by a compiler, the instrumented code including at least one call to un-instrumented code. The compiler can determine the at least one call to un-instrumented code is a next call to be executed. A resume tracing instruction can be inserted into the instrumented code prior to the at least one call to the un-instrumented code. The resume tracing instruction can be executed to selectively add processor tracing to the at least one call to the un-instrumented code, and the at least one call to the un-instrumented code can be executed.

    Hardened safe stack for return oriented programming attack mitigation
    13.
    发明授权
    Hardened safe stack for return oriented programming attack mitigation 有权

    公开(公告)号：US10795997B2

    公开(公告)日：2020-10-06

    申请号：US15629458

    申请日：2017-06-21

    Applicant: INTEL CORPORATION

    Inventor： Michael Lemay

    IPC: G06F21/56 ,  G06F21/55 ,  G06F21/52 ,  G06F21/54

    Abstract: Techniques and computing devices for mitigating return-oriented programming (ROP) attacks are described. A hardened stack and an unhardened stack are provided. The hardened stack can include indications of return addresses while the unhardened stack can include all other memory allocations. A stack hardening instruction can be inserted before unhardened instructions (e.g., instructions that are themselves not authorized to access the hardened stack). The stack hardening instruction determines whether the unhardened instruction accessed memory outside the unhardened stack and generates a fault based on the determination. A register can be provided to include an indication of an address span of the unsafe stack. The stack hardening instruction can determine whether the unhardened instruction accessed a memory location outside the address range specified in the register and generate a fault accordingly.

    Technologies for execute only transactional memory
    14.
    发明授权
    Technologies for execute only transactional memory 有权

    公开(公告)号：US10558582B2

    公开(公告)日：2020-02-11

    申请号：US14974972

    申请日：2015-12-18

    Applicant: Intel Corporation

    Inventor： David M. Durham ,  Michael Lemay ,  Men Long

    IPC: G06F12/00 ,  G06F12/1027 ,  G06F9/30 ,  G06F12/14

    Abstract: Technologies for execute only transactional memory include a computing device with a processor and a memory. The processor includes an instruction translation lookaside buffer (iTLB) and a data translation lookaside buffer (dTLB). In response to a page miss, the processor determines whether a page physical address is within an execute only transactional (XOT) range of the memory. If within the XOT range, the processor may populate the iTLB with the page physical address and prevent the dTLB from being populated with the page physical address. In response to an asynchronous change of control flow such as an interrupt, the processor determines whether a last iTLB translation is within the XOT range. If within the XOT range, the processor clears or otherwise secures the processor register state. The processor ensures that an XOT range starts execution at an authorized entry point. Other embodiments are described and claimed.

    Cryptographic operations for secure page mapping in a virtual machine environment
    15.
    发明授权
    Cryptographic operations for secure page mapping in a virtual machine environment 有权

    公开(公告)号：US10152612B2

    公开(公告)日：2018-12-11

    申请号：US14866211

    申请日：2015-09-25

    Applicant: INTEL CORPORATION

    Inventor： Michael Lemay

    IPC: G06F9/32 ,  G06F9/455 ,  H04L9/32 ,  G06F21/72 ,  G06F21/79

    Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for secure memory page mapping in a virtual machine (VM) environment. The system may include a processor configured to execute a virtual machine monitor (VMM). The VMM may be configured to maintain a table of cryptographic keys and associate a token with one of the memory pages to be mapped from a guest linear address (GLA) to a guest physical address (GPA). The token may include a key identifier (key ID) associated with one of the cryptographic keys, and an authentication code based on the GLA, the GPA, and one of the cryptographic keys. The system may also include a page walk processor configured to validate the token to indicate that the memory page associated with the token is authorized to be mapped from the GLA to the GPA.

    Apparatus and method for efficient process-based compartmentalization
    17.
    发明授权
    Apparatus and method for efficient process-based compartmentalization 有权

    公开(公告)号：US11741018B2

    公开(公告)日：2023-08-29

    申请号：US17873668

    申请日：2022-07-26

    Applicant: Intel Corporation

    Inventor： David M. Durham ,  Jacob Doweck ,  Michael Lemay ,  Deepak Gupta

    IPC: G06F12/10 ,  G06F12/1027

    CPC classification number: G06F12/1027 ,  G06F2212/681

    Abstract: An apparatus and method for efficient process-based compartmentalization. For example, one embodiment of a processor comprises: execution circuitry to execute instructions and process data; memory management circuitry coupled to the execution circuitry, the memory management circuitry to manage access to a system memory by a plurality of related processes using one or more process-specific translation structures and one or more shared translation structures to be shared by the related processes; and one or more control registers to store a process-specific base address pointer associated with a first process of the plurality of related processes and to store a shared base address pointer to identify the shared translation structures; wherein the memory management circuitry is to use the process-specific base address pointer in combination with a first linear address provided by the first process to walk the process-specific translation structures to identify any permissions and/or physical address associated with the first linear address, wherein if permissions are identified, the memory management circuitry is to use the permissions in place of any permissions specified in the shared translation structures.

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