公开(公告)号：US12197949B2

公开(公告)日：2025-01-14

申请号：US17877636

申请日：2022-07-29

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Kshitij Doshi ,  Ned M. Smith

IPC: H04L29/06 ,  G06F9/455 ,  G06F9/48 ,  G06F9/50 ,  G06F11/30 ,  G06F16/23 ,  G06F16/27 ,  G06F21/60 ,  G06F21/62 ,  H04L9/06 ,  H04L9/08 ,  H04L9/32 ,  H04L12/66 ,  H04L41/12 ,  H04L47/70 ,  H04L67/52 ,  H04L67/60 ,  H04L9/00

Abstract: Technologies for providing attestation for function as a service flavors include a compute device including circuitry configured to obtain function definition data indicative of a set of operations to be performed in a function and a set of hardware resources to be utilized by the function, execute a benchmark operation to produce benchmark data indicative of a measured performance of the function, and sign the function definition data and the benchmark data to produce function flavor data. The circuitry is also configured to provide the function flavor data to one or more other compute devices for validation that the function, when executed on the hardware resources, provides the measured performance and write, to a distributed ledger, the function flavor data.

公开(公告)号：US12045652B2

公开(公告)日：2024-07-23

申请号：US17726322

申请日：2022-04-21

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Kshitij Doshi ,  Suraj Prebhakaran ,  Ned M. Smith

IPC: G06F9/50 ,  G06F9/455 ,  G06F9/48 ,  G06F11/30 ,  G06F16/23 ,  G06F16/27 ,  G06F21/60 ,  G06F21/62 ,  H04L9/00 ,  H04L9/06 ,  H04L9/08 ,  H04L9/32 ,  H04L12/66 ,  H04L41/12 ,  H04L47/70 ,  H04L67/52 ,  H04L67/60

CPC classification number: G06F9/5005 ,  G06F9/455 ,  G06F9/45533 ,  G06F9/45558 ,  G06F9/48 ,  G06F9/4806 ,  G06F9/4843 ,  G06F9/485 ,  G06F9/4856 ,  G06F9/4862 ,  G06F9/4881 ,  G06F9/4893 ,  G06F9/50 ,  G06F9/5011 ,  G06F9/5027 ,  G06F9/5033 ,  G06F9/5044 ,  G06F9/505 ,  G06F9/5061 ,  G06F9/5072 ,  G06F9/5077 ,  G06F9/5083 ,  G06F9/5088 ,  G06F9/5094 ,  G06F11/30 ,  G06F16/2365 ,  G06F16/27 ,  G06F21/602 ,  G06F21/62 ,  H04L9/0637 ,  H04L9/0827 ,  H04L9/3247 ,  H04L12/66 ,  H04L41/12 ,  H04L47/82 ,  H04L67/52 ,  H04L67/60 ,  G06F2009/45562 ,  G06F2009/4557 ,  H04L9/50

Abstract: Technologies for batching requests in an edge infrastructure include a compute device including circuitry configured to obtain a request for an operation to be performed at an edge location. The circuitry is also configured to determine, as a function of a parameter of the obtained request, a batch that the obtained request is to be assigned to. The batch includes a one or more requests for operations to be performed at an edge location. The circuitry is also configured to assign the batch to a cloudlet at an edge location. The cloudlet includes a set of resources usable to execute the operations requested in the batch.

公开(公告)号：US20240112506A1

公开(公告)日：2024-04-04

申请号：US17936438

申请日：2022-09-29

Applicant: Intel Corporation

Inventor： Ned M. Smith ,  S M Iftekharul Alam ,  Ignacio J. Alvarez ,  Kshitij Doshi ,  Francesc Guim Bernat ,  Satish Jha ,  Arvind Merwaday ,  Vesh Raj Sharma Banjade ,  Kathiravetpillai Sivanesan

IPC: G07C5/00 ,  H04W74/00

CPC classification number: G07C5/008 ,  H04W74/002

Abstract: A DTaaS architecture is described to support communication-side optimization and to reduce communication overhead while meeting necessary reliability and latency requirements. The disclosure describe techniques for utilizing DT resources for V2X environments using both virtual and physical “twin” resources to achieve improved resiliency. Moreover, to optimize redundancy costs, the ratio of virtual DT nodes to physical DT nodes may be asymmetrical. An asymmetric approach to DT redundancies involving both virtual and physical resources enables greater flexibility in managing deployment costs.

公开(公告)号：US11922220B2

公开(公告)日：2024-03-05

申请号：US17255588

申请日：2019-04-16

Applicant: Intel Corporation

Inventor： Mohammad R. Haghighat ,  Kshitij Doshi ,  Andrew J. Herdrich ,  Anup Mohan ,  Ravishankar R. Iyer ,  Mingqiu Sun ,  Krishna Bhuyan ,  Teck Joo Goh ,  Mohan J. Kumar ,  Michael Prinke ,  Michael Lemay ,  Leeor Peled ,  Jr-Shian Tsai ,  David M. Durham ,  Jeffrey D. Chamberlain ,  Vadim A. Sukhomlinov ,  Eric J. Dahlen ,  Sara Baghsorkhi ,  Harshad Sane ,  Areg Melik-Adamyan ,  Ravi Sahita ,  Dmitry Yurievich Babokin ,  Ian M. Steiner ,  Alexander Bachmutsky ,  Anil Rao ,  Mingwei Zhang ,  Nilesh K. Jain ,  Amin Firoozshahian ,  Baiju V. Patel ,  Wenyong Huang ,  Yeluri Raghuram

IPC: G06F9/50 ,  G06F9/52 ,  G06F11/30 ,  G06F11/34 ,  G06F21/53 ,  G06F21/56 ,  G06F21/60 ,  G06N20/00

CPC classification number: G06F9/5061 ,  G06F9/52 ,  G06F11/302 ,  G06F11/3495 ,  G06F21/53 ,  G06F21/604 ,  G06F21/56 ,  G06F2209/521 ,  G06F2221/033 ,  G06N20/00

Abstract: Embodiments of systems, apparatuses and methods provide enhanced function as a service (FaaS) to users, e.g., computer developers and cloud service providers (CSPs). A computing system configured to provide such enhanced FaaS service include one or more controls architectural subsystems, software and orchestration subsystems, network and storage subsystems, and security subsystems. The computing system executes functions in response to events triggered by the users in an execution environment provided by the architectural subsystems, which represent an abstraction of execution management and shield the users from the burden of managing the execution. The software and orchestration subsystems allocate computing resources for the function execution by intelligently spinning up and down containers for function code with decreased instantiation latency and increased execution scalability while maintaining secured execution. Furthermore, the computing system enables customers to pay only when their code gets executed with a granular billing down to millisecond increments.

公开(公告)号：US11704424B2

公开(公告)日：2023-07-18

申请号：US17386015

申请日：2021-07-27

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Mark Schmisseur ,  Kshitij Doshi ,  Kapil Sood ,  Tarun Viswanathan

IPC: G06F21/62 ,  G06F21/60 ,  H04L9/08 ,  H04L67/12 ,  H04W12/08 ,  H04W12/02 ,  H04L9/40

CPC classification number: G06F21/6218 ,  G06F21/602 ,  H04L9/083 ,  H04L9/085 ,  H04L9/0891 ,  H04L9/0894 ,  H04L63/0442 ,  H04L67/12 ,  H04W12/02 ,  H04W12/08 ,  H04L2209/805

Abstract: An embodiment of a semiconductor apparatus may include technology to receive data with a unique identifier, and bypass encryption logic of a media controller based on the unique identifier. Other embodiments are disclosed and claimed.

公开(公告)号：US20220357989A1

公开(公告)日：2022-11-10

申请号：US17552833

申请日：2021-12-16

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Ned Smith ,  Kshitij Doshi ,  Raghu Kondapalli ,  Alexander Bachmutsky

IPC: G06F9/50 ,  H04L9/08 ,  H04L9/40

Abstract: Technologies for providing a multi-tenant local breakout switching and dynamic load balancing include a network device to receive network traffic that includes a packet associated with a tenant. Upon a determination that the packet is encrypted, a secret key associated with the tenant is retrieved. The network device decrypts a payload from the packet using the secret key. The payload is indicative of one or more characteristics associated with network traffic. The network device evaluates the characteristics and determines whether the network traffic is associated with a workload requesting compute from a service hosted by a network platform. If so, the network device forwards the network traffic to the service.

公开(公告)号：US20220318064A1

公开(公告)日：2022-10-06

申请号：US17726322

申请日：2022-04-21

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Kshitij Doshi ,  Suraj Prebhakaran ,  Ned M. Smith

IPC: G06F9/50 ,  G06F16/23 ,  H04L9/06 ,  G06F16/27 ,  H04L9/32 ,  H04L41/12 ,  H04L47/70 ,  G06F21/60 ,  H04L9/08 ,  G06F21/62 ,  H04L67/52 ,  H04L67/60 ,  G06F9/455 ,  G06F9/48 ,  G06F11/30 ,  H04L12/66

Abstract: Technologies for batching requests in an edge infrastructure include a compute device including circuitry configured to obtain a request for an operation to be performed at an edge location. The circuitry is also configured to determine, as a function of a parameter of the obtained request, a batch that the obtained request is to be assigned to. The batch includes a one or more requests for operations to be performed at an edge location. The circuitry is also configured to assign the batch to a cloudlet at an edge location. The cloudlet includes a set of resources usable to execute the operations requested in the batch.

公开(公告)号：US11444846B2

公开(公告)日：2022-09-13

申请号：US16368980

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Kapil Sood ,  Tarun Viswanathan ,  Kshitij Doshi ,  Timothy Verrall ,  Ned M. Smith ,  Manish Dave ,  Alex Vul

IPC: H04L41/00 ,  H04L9/40 ,  H04L41/5003 ,  H04L41/0893 ,  G06F21/57

Abstract: Technologies for accelerated orchestration and attestation include multiple edge devices. An edge appliance device performs an attestation process with each of its components to generate component certificates. The edge appliance device generates an appliance certificate that is indicative of the component certificates and a current utilization of the edge appliance device and provides the appliance certificate to a relying party. The relying party may be an edge orchestrator device. The edge orchestrator device receives a workload scheduling request with a service level agreement requirement. The edge orchestrator device verifies the appliance certificate and determines whether the service level agreement requirement is satisfied based on the appliance certificate. If satisfied, the workload is scheduled to the edge appliance device. Attestation and generation of the appliance certificate by the edge appliance device may be performed by an accelerator of the edge appliance device. Other embodiments are described and claimed.

公开(公告)号：US20220237033A1

公开(公告)日：2022-07-28

申请号：US17666366

申请日：2022-02-07

Applicant: Intel Corporation

Inventor： Evan Custodio ,  Francesc Guim Bernat ,  Suraj Prabhakaran ,  Trevor Cooper ,  Ned M. Smith ,  Kshitij Doshi ,  Petar Torre

IPC: G06F9/50

Abstract: Technologies for migrating data between edge accelerators hosted on different edge locations include a device hosted on a present edge location. The device includes one or more processors to: receive a workload from a requesting device, determine one or more accelerator devices hosted on the present edge location to perform the workload, and transmit the workload to the one or more accelerator devices to process the workload. The one or more processor is further to determine whether to perform data migration from the one or more accelerator devices to one or more different edge accelerator devices hosted on a different edge location, and send, in response to a determination to perform the data migration, a request to the one or more accelerator devices on the present edge location for transformed workload data to be processed by the one or more different edge accelerator devices.

公开(公告)号：US11354240B2

公开(公告)日：2022-06-07

申请号：US16907729

申请日：2020-06-22

Applicant: Intel Corporation

Inventor： Vadim Sukhomlinov ,  Kshitij Doshi

IPC: G06F12/08 ,  G06F12/0804 ,  G06F12/0875 ,  G06F12/0891

Abstract: The present disclosure is directed to systems and methods that include cache operation storage circuitry that selectively enables/disables the Cache Line Flush (CLFLUSH) operation. The cache operation storage circuitry may also selectively replace the CLFLUSH operation with one or more replacement operations that provide similar functionality but beneficially and advantageously prevent an attacker from placing processor cache circuitry in a known state during a timing-based, side channel attack such as Spectre or Meltdown. The cache operation storage circuitry includes model specific registers (MSRs) that contain information used to determine whether to enable/disable CLFLUSH functionality. The cache operation storage circuitry may include model specific registers (MSRs) that contain information used to select appropriate replacement operations such as Cache Line Demote (CLDEMOTE) and/or Cache Line Write Back (CLWB) to selectively replace CLFLUSH operations.