公开(公告)号：US20240355641A1

公开(公告)日：2024-10-24

申请号：US18761453

申请日：2024-07-02

Applicant: Intel Corporation

Inventor： Sri Chaitra Jyotsna Chavali ,  Siddharth K. Alur ,  Lilia May ,  Amanda E. Shuckman

IPC: H01L21/48 ,  H01L23/498

CPC classification number: H01L21/4857 ,  H01L23/49822 ,  H01L23/49827

Abstract: Generally discussed herein are systems, devices, and methods that include an organic high-density interconnect structure and techniques for making the same. According to an example a method can include forming one or more low-density buildup layers on a core, conductive interconnect material of the one or more low-density buildup layers electrically and mechanically connected to conductive interconnect material of the core, forming one or more high-density buildup layers on an exposed low-density buildup layer of the one or more low-density buildup layers, conductive interconnect material of the high-density buildup layers electrically and mechanically connected to the conductive interconnect material of the one or more low-density buildup layers, and forming another low-density buildup layer on and around an exposed high-density buildup layer of the one or more high-density buildup layers.

公开(公告)号：US11075130B2

公开(公告)日：2021-07-27

申请号：US16481216

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Lisa Ying Ying Chen ,  Lauren Ashley Link ,  Robert Alan May ,  Amruthavalli Pallavi Alur ,  Kristof Kuwawi Darmawikarta ,  Siddharth K. Alur ,  Sri Ranga Sai Boyapati ,  Andrew James Brown ,  Lilia May

IPC: H01L21/48 ,  H01L23/15 ,  C04B35/622 ,  C04B35/64 ,  H01L23/498 ,  G03F7/16 ,  G03F7/20 ,  G03F7/32

Abstract: Semiconductor packages including package substrates having polymer-derived ceramic cores are described. In an example, a package substrate includes a core layer including a polymer-derived ceramic. The polymer-derived ceramic may include filler particles to control shrinkage and reduce warpage of the core layer during fabrication and use of the package substrate. The core layer may include counterbores or blind holes to embed a contact pad or an electrical interconnect in the core layer. A semiconductor die may be mounted on the package substrate and may be electrically connected to the contact pad or the electrical interconnect.

公开(公告)号：US20200312675A1

公开(公告)日：2020-10-01

申请号：US16901172

申请日：2020-06-15

Applicant: Intel Corporation

Inventor： Sri Chaitra Jyotsna Chavali ,  Siddharth K. Alur ,  Lilia May ,  Amanda E. Amanda

IPC: H01L21/48 ,  H01L23/498

Abstract: Generally discussed herein are systems, devices, and methods that include an organic high density interconnect structure and techniques for making the same. According to an example a method can include forming one or more low density buildup layers on a core, conductive interconnect material of the one or more low density buildup layers electrically and mechanically connected to conductive interconnect material of the core, forming one or more high density buildup layers on an exposed low density buildup layer of the one or more low density buildup layers, conductive interconnect material of the high density buildup layers electrically and mechanically connected to the conductive interconnect material of the one or more low density buildup layers, and forming another low density buildup layer on and around an exposed high density buildup layer of the one or more high density buildup layers.

公开(公告)号：US10685850B2

公开(公告)日：2020-06-16

申请号：US16305743

申请日：2016-06-30

Applicant: Intel Corporation

Inventor： Sri Chaitra Jyotsna Chavali ,  Siddharth K. Alur ,  Lilia May ,  Amanda E. Schuckman

IPC: H01L21/48 ,  H01L23/498

Abstract: Generally discussed herein are systems, devices, and methods that include an organic high density interconnect structure and techniques for making the same. According to an example a method can include forming one or more low density buildup layers on a core, conductive interconnect material of the one or more low density buildup layers electrically and mechanically connected to conductive interconnect material of the core, forming one or more high density buildup layers on an exposed low density buildup layer of the one or more low density buildup layers, conductive interconnect material of the high density buildup layers electrically and mechanically connected to the conductive interconnect material of the one or more low density buildup layers, and forming another low density buildup layer on and around an exposed high density buildup layer of the one or more high density buildup layers.

公开(公告)号：US10553453B2

公开(公告)日：2020-02-04

申请号：US16317789

申请日：2016-07-14

Applicant: Intel Corporation

Inventor： Sri Chaitra Chavali ,  Siddharth K. Alur ,  Amanda E. Schuckman ,  Amruthavalli Palla Alur ,  Islam A. Salama ,  Yikang Deng ,  Kristof Darmawikarta

IPC: H05K1/03 ,  H05K3/00 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L23/522 ,  H01L23/532

Abstract: Various embodiments of the disclosure are directed to a semiconductor package and a method for fabrication of the semiconductor package. Further, disclosed herein are systems and methods that are directed to using a photoimagable dielectric (PID) layer with substantially similar mechanical properties as that of a mold material. The disclosure can be used, for example, in the context of bumpless laserless embedded substrate structures (BLESS) technology for wafer/panel level redistribution layer (RDL) and/or fan-out packaging applications. The disclosed embodiments may reduce the need for multiple dry resist film (DFR) lamination steps during various processing steps for semiconductor packaging and can also facilitate multiple layer counts due to the availability of thin PID materials.

公开(公告)号：US09728500B2

公开(公告)日：2017-08-08

申请号：US14972936

申请日：2015-12-17

Applicant: Intel Corporation

Inventor： Siddharth K. Alur ,  Sri Chaitra J. Chavali ,  Robert A. May ,  Whitney M. Bryks

IPC: H01L23/52 ,  H01L23/528 ,  H01L21/768 ,  H01L21/3105 ,  H01L21/3205 ,  H01L21/02

CPC classification number: H01L23/528 ,  H01L21/02118 ,  H01L21/02164 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/31058 ,  H01L21/32051 ,  H01L21/321 ,  H01L21/76834 ,  H01L21/76841 ,  H01L23/53228 ,  H01L23/53295

Abstract: Embodiments of the present disclosure describe an integrated circuit and associated fabrication techniques and configurations, which may include forming on at least one of a metal layer or a polymer layer of an integrated circuit die a surface layer that includes an adhesion-functional group, and applying to the surface layer a next layer to adhere to the surface layer with the adhesion-functional group. In embodiments wherein the at least one of the metal layer or the polymer layer is a polymer layer, forming the surface layer may include copolymerizing on the polymer layer a polar monomer that includes the adhesion-functional group. In embodiments wherein the at least one of the metal layer or the polymer layer is a metal layer, forming the surface layer may include forming on the metal layer a self-assembled monolayer that includes amine group terminations. Other embodiments may be described and/or claimed.

公开(公告)号：US12062551B2

公开(公告)日：2024-08-13

申请号：US18118835

申请日：2023-03-08

Applicant: Intel Corporation

Inventor： Sri Chaitra Jyotsna Chavali ,  Siddharth K. Alur ,  Lilia May ,  Amanda E. Schuckman

IPC: H01L21/48 ,  H01L23/498

CPC classification number: H01L21/4857 ,  H01L23/49822 ,  H01L23/49827

Abstract: Generally discussed herein are systems, devices, and methods that include an organic high density interconnect structure and techniques for making the same. According to an example a method can include forming one or more low density buildup layers on a core, conductive interconnect material of the one or more low density buildup layers electrically and mechanically connected to conductive interconnect material of the core, forming one or more high density buildup layers on an exposed low density buildup layer of the one or more low density buildup layers, conductive interconnect material of the high density buildup layers electrically and mechanically connected to the conductive interconnect material of the one or more low density buildup layers, and forming another low density buildup layer on and around an exposed high density buildup layer of the one or more high density buildup layers.

公开(公告)号：US10741947B2

公开(公告)日：2020-08-11

申请号：US15868169

申请日：2018-01-11

Applicant: Intel Corporation

Inventor： Amruthavalli Pallavi Alur ,  Siddharth K. Alur ,  Liwei Cheng ,  Lauren A. Link ,  Jonathan L. Rosch ,  Sai Vadlamani ,  Cheng Xu

IPC: H01R12/71 ,  H01R43/16 ,  H01R13/24 ,  H01R12/70 ,  H05K3/42 ,  H01R12/58 ,  H01R12/52

Abstract: An electronic interconnect may include a substrate. The substrate may include a passageway in the substrate. The passageway may extend from a first surface of the substrate toward a second surface of the substrate. The passageway may be closed at an end of the passageway. The electronic interconnect may include a plated through hole socket coupled to the passageway. The electronic interconnect may include a contact. The contact may include a pin. The pin may be configured to engage with the plated through hole socket. The electronic interconnect may include a solder ball. The solder ball may be coupled to the plated through hole socket.

公开(公告)号：US20190393129A1

公开(公告)日：2019-12-26

申请号：US16540177

申请日：2019-08-14

Applicant: Intel Corporation

Inventor： Siddharth K. Alur ,  Sri Chaitra Jyotsna Chavali

IPC: H01L23/373 ,  H01L23/498 ,  H01L23/367 ,  H01L21/48

Abstract: According to various embodiments of the present disclosure, an electrically conductive pillar having a substrate is disclosed. The electrically conductive pillar can comprise a first portion, second portion and a third portion. The first portion and/or third portion can be formed of an electrically conductive material that can be the same or different. The second portion can be intermediate and abut both the first portion and the third portion. The second portion can comprise a solder element formed of a second electrically conductive material that differs from the electrically conductive material and has a second stiffness less than a stiffness of the electrically conductive material.

公开(公告)号：US10424530B1

公开(公告)日：2019-09-24

申请号：US16014077

申请日：2018-06-21

Applicant: Intel Corporation

Inventor： Siddharth K. Alur ,  Sri Chaitra Jyotsna Chavali

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/373 ,  H01L23/498 ,  H01L21/48 ,  H01L23/367

Abstract: According to various embodiments of the present disclosure, an electrically conductive pillar having a substrate is disclosed. The electrically conductive pillar can comprise a first portion, second portion and a third portion. The first portion and/or third portion can be formed of an electrically conductive material that can be the same or different. The second portion can be intermediate and abut both the first portion and the third portion. The second portion can comprise a solder element formed of a second electrically conductive material that differs from the electrically conductive material and has a second stiffness less than a stiffness of the electrically conductive material.