公开(公告)号：US20180005988A1

公开(公告)日：2018-01-04

申请号：US15196884

申请日：2016-06-29

Applicant: International Business Machines Corporation

Inventor： Hariklia Deligianni ,  Devendra K. Sadana ,  Edmund J. Sprogis ,  Naigang Wang

IPC: H01L25/065 ,  H01L27/092 ,  H01L21/48 ,  H01L49/02 ,  H01L21/8238

CPC classification number: H01L25/0657 ,  H01L21/4853 ,  H01L21/8238 ,  H01L27/092 ,  H01L28/10 ,  H01L2224/11 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2924/10253 ,  H01L2924/1033 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/19042 ,  H01L2924/19104

Abstract: DC-DC power converters with GaN switches, magnetic inductors and CMOS power drivers integrated through face-to-face wafer bonding techniques are provided. In one aspect, an integrated DC-DC power converter includes: a Si CMOS chip having at least one Si CMOS transistor formed thereon; a GaN switch chip, bonded to the Si CMOS chip in a face-to-face manner, having at least one GaN transistor formed thereon; and an on-chip magnetic inductor present either on the Si CMOS chip or on the GaN switch chip. A method of forming an integrated DC-DC power converter is also provided.

公开(公告)号：US09819269B1

公开(公告)日：2017-11-14

申请号：US15477457

申请日：2017-04-03

Applicant: International Business Machines Corporation

Inventor： Hariklia Deligianni ,  Devendra K. Sadana ,  Edmund J. Sprogis ,  Naigang Wang

IPC: H01L29/15 ,  H02M3/158 ,  H01L29/20 ,  H01L29/205 ,  H01L23/498 ,  H01L49/02 ,  H01L29/778 ,  H01L23/00 ,  H01L25/07 ,  H01L21/288 ,  H01L23/532 ,  H01L23/522 ,  H01L29/66 ,  H01L21/683

CPC classification number: H02M3/158 ,  H01L21/288 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/8221 ,  H01L23/3114 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/53228 ,  H01L24/09 ,  H01L24/16 ,  H01L24/81 ,  H01L25/074 ,  H01L27/0688 ,  H01L28/10 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/7787 ,  H01L2221/6834 ,  H01L2224/03002 ,  H01L2224/05147 ,  H01L2224/08145 ,  H01L2224/11002 ,  H01L2224/16145 ,  H01L2224/16157 ,  H01L2224/16165 ,  H01L2224/16225 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/1033 ,  H01L2924/10344 ,  H01L2924/13064 ,  H01L2924/1426 ,  H01L2924/19011 ,  H01L2924/19042 ,  H01L2924/19102 ,  H02M3/02 ,  Y02B70/1483

Abstract: Techniques for integrating DC-DC power converters with other on-chip circuitry are provided. In one aspect, an integrated DC-DC power converter includes: a GaN transistor chip having at least one GaN switch formed thereon; an interposer chip, bonded to the GaN transistor chip, having at least one power driver transistor formed thereon; TSVs present in the interposer chip adjacent to the power driver transistor and which connect the power driver transistor to the GaN switch; and an on-chip magnetic inductor formed either on the GaN transistor chip or on the interposer chip. A method of forming a fully integrated DC-DC power converter is also provided.

公开(公告)号：US09654004B1

公开(公告)日：2017-05-16

申请号：US15185723

申请日：2016-06-17

Applicant: International Business Machines Corporation

Inventor： Hariklia Deligianni ,  Devendra K. Sadana ,  Edmund J. Sprogis ,  Naigang Wang

IPC: H01L21/4763 ,  H02M3/158 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L23/498 ,  H01L23/31 ,  H01L29/66 ,  H01L21/48 ,  H01L21/56 ,  H01L27/06 ,  H01L21/822 ,  H01L49/02

CPC classification number: H02M3/158 ,  H01L21/288 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/8221 ,  H01L23/3114 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/53228 ,  H01L24/09 ,  H01L24/16 ,  H01L24/81 ,  H01L25/074 ,  H01L27/0688 ,  H01L28/10 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/7787 ,  H01L2221/6834 ,  H01L2224/03002 ,  H01L2224/05147 ,  H01L2224/08145 ,  H01L2224/11002 ,  H01L2224/16145 ,  H01L2224/16157 ,  H01L2224/16165 ,  H01L2224/16225 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/1033 ,  H01L2924/10344 ,  H01L2924/13064 ,  H01L2924/1426 ,  H01L2924/19011 ,  H01L2924/19042 ,  H01L2924/19102 ,  H02M3/02 ,  Y02B70/1483

Abstract: Techniques for integrating DC-DC power converters with other on-chip circuitry are provided. In one aspect, an integrated DC-DC power converter includes: a GaN transistor chip having at least one GaN switch formed thereon; an interposer chip, bonded to the GaN transistor chip, having at least one power driver transistor formed thereon; TSVs present in the interposer chip adjacent to the power driver transistor and which connect the power driver transistor to the GaN switch; and an on-chip magnetic inductor formed either on the GaN transistor chip or on the interposer chip. A method of forming a fully integrated DC-DC power converter is also provided.

公开(公告)号：US20130147015A1

公开(公告)日：2013-06-13

申请号：US13765105

申请日：2013-02-12

Applicant: International Business Machines Corporation

Inventor： James S. Nakos ,  Edmund J. Sprogis ,  Anthony K. Stamper

IPC: H01L49/02

CPC classification number: H01L28/40 ,  H01L29/66181 ,  H01L29/945

Abstract: Solutions for forming a silicided deep trench decoupling capacitor are disclosed. In one aspect, a method of forming a semiconductor device includes: forming an outer trench in a silicon substrate, the forming exposing portions of the silicon substrate below an upper surface of the silicon substrate; depositing a dielectric liner layer inside the trench; depositing a doped polysilicon layer over the dielectric liner layer, the doped polysilicon layer forming an inner trench in the silicon substrate; forming a silicide layer over a portion of the doped polysilicon layer; forming an intermediate contact layer within the inner trench; and forming a contact over a portion of the intermediate contact layer and a portion of the silicide layer.

Abstract translation: 公开了用于形成硅化深沟槽去耦电容器的解决方案。 一方面，一种形成半导体器件的方法包括：在硅衬底中形成外部沟槽，所述硅衬底的所述成形暴露部分位于所述硅衬底的上表面下方; 在沟槽内沉积介电衬垫层; 在所述介​​质衬底层上沉积掺杂多晶硅层，所述掺杂多晶硅层在所述硅衬底中形成内部沟槽; 在所述掺杂多晶硅层的一部分上形成硅化物层; 在所述内沟槽内形成中间接触层; 以及在所述中间接触层的一部分和所述硅化物层的一部分上形成接触。

公开(公告)号：US20150235891A1

公开(公告)日：2015-08-20

申请号：US14183989

申请日：2014-02-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： John J. Garant ,  Jonathan H. Griffith ,  Brittany L. Hedrick ,  Edmund J. Sprogis

IPC: H01L21/683 ,  B32B38/10 ,  B32B37/24 ,  H01L21/02 ,  B32B37/26

CPC classification number: H01L21/6835 ,  B32B37/24 ,  B32B38/10 ,  B32B2037/246 ,  B32B2315/08 ,  B32B2457/14 ,  B81C1/00666 ,  B81C2201/0167 ,  H01L2221/68304 ,  H01L2221/68327

Abstract: A wafer handler with a removable bow compensating layer and methods of manufacture is disclosed. The method includes forming at least one layer of stressed material on a front side of a wafer handler. The method further includes forming another stressed material on a backside of the wafer handler which counter balances the at least one layer of stressed material on the front side of the wafer handler, thereby decreasing an overall bow of the wafer handler.

Abstract translation: 公开了具有可拆卸弓形补偿层的晶片处理器和制造方法。 该方法包括在晶片处理器的正面上形成至少一层应力材料。 该方法还包括在晶片处理器的背面上形成另一个应力材料，该材料在晶片处理器的前侧平衡至少一层应力材料，从而减小晶片处理器的整体弓形。

公开(公告)号：US20140209908A1

公开(公告)日：2014-07-31

申请号：US14242203

申请日：2014-04-01

Applicant: International Business Machines Corporation

Inventor： Edward C. Cooney, III ,  James S. Dunn ,  Dale W. Martin ,  Charles S. Musante ,  BethAnn Rainey Lawrence ,  Leathen Shi ,  Edmund J. Sprogis ,  Cornelia K. Tsang

IPC: H01L23/482 ,  H01L21/66

CPC classification number: H01L23/4825 ,  H01L21/6835 ,  H01L21/76819 ,  H01L22/32 ,  H01L22/34 ,  H01L23/5223 ,  H01L23/5283 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L24/80 ,  H01L24/81 ,  H01L29/1054 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2224/0361 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05187 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05687 ,  H01L2224/06181 ,  H01L2224/08225 ,  H01L2224/131 ,  H01L2224/73251 ,  H01L2224/80011 ,  H01L2224/80013 ,  H01L2224/80075 ,  H01L2224/80203 ,  H01L2224/804 ,  H01L2224/80487 ,  H01L2224/80896 ,  H01L2224/80907 ,  H01L2224/80948 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/15788 ,  H01L2924/014 ,  H01L2224/08 ,  H01L2224/16 ,  H01L2924/05432 ,  H01L2924/053 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/04941 ,  H01L2924/00 ,  H01L2224/05552

Abstract: Methods for bonding substrate surfaces, bonded substrate assemblies, and design structures for a bonded substrate assembly. Device structures of a product chip are formed using a first surface of a device substrate. A wiring layer of an interconnect structure for the device structures is formed on the product chip. The wiring layer is planarized. A temporary handle wafer is removably bonded to the planarized wiring layer. In response to removably bonding the temporary handle wafer to the planarized first wiring layer, a second surface of the device substrate, which is opposite to the first surface, is bonded to a final handle substrate. The temporary handle wafer is then removed from the assembly.

Abstract translation: 用于粘结衬底表面，键合衬底组件和用于键合衬底组件的设计结构的方法。 使用器件基板的第一表面形成产品芯片的器件结构。 在产品芯片上形成用于器件结构的互连结构的布线层。 布线层被平坦化。 临时处理晶片可移除地结合到平坦化的布线层。 响应于将临时手柄晶片可移除地结合到平坦化的第一布线层，与第一表面相对的器件基板的第二表面被结合到最终的手柄基板。 然后将临时手柄晶片从组件中取出。

公开(公告)号：US08785289B2

公开(公告)日：2014-07-22

申请号：US13975519

申请日：2013-08-26

Applicant: International Business Machines Corporation

Inventor： Tae Hong Kim ,  Michael F. McAllister ,  Michael J. Shapiro ,  Edmund J. Sprogis

IPC: H01L21/20 ,  H01L21/44

CPC classification number: H01L28/40 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/642 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/13025 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A capacitor in a semiconductor substrate employs a conductive through-substrate via (TSV) as an inner electrode and a columnar doped semiconductor region as an outer electrode. The capacitor provides a large decoupling capacitance in a small area, and does not impact circuit density or a Si3D structural design. Additional conductive TSV's can be provided in the semiconductor substrate to provide electrical connection for power supplies and signal transmission therethrough. The capacitor has a lower inductance than a conventional array of capacitors having comparable capacitance, thereby enabling reduction of high frequency noise in the power supply system of stacked semiconductor chips.

Abstract translation: 半导体衬底中的电容器采用导电贯穿衬底通孔（TSV）作为内部电极和柱状掺杂半导体区域作为外部电极。 电容器在小面积上提供大的去耦电容，并且不影响电路密度或Si3D结构设计。 可以在半导体衬底中提供附加的导电TSV，以提供用于电源和通过其的信号传输的电连接。 电容器具有比具有相当电容的传统电容器阵列更低的电感，从而能够降低层叠半导体芯片的电源系统中的高频噪声。