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    Transistor with improved avalanche breakdown behavior
    16.
    发明授权
    Transistor with improved avalanche breakdown behavior 有权

    公开(公告)号：US09673320B2

    公开(公告)日：2017-06-06

    申请号：US15182120

    申请日：2016-06-14

    Applicant: Infineon Technologies AG

    Inventor： Andreas Meiser ,  Till Schloesser

    IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/66

    CPC classification number: H01L29/7819 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/408 ,  H01L29/41766 ,  H01L29/66696 ,  H01L29/66704 ,  H01L29/7825

    Abstract: A transistor cell includes a drift region, a source region, a body region, and a drain region that is laterally spaced apart from the source region. A gate electrode is adjacent the body region. A field electrode is arranged in the drift region. A source electrode is connected to the source region and the body region, and a drain electrode is connected to the drain region. An avalanche bypass structure is coupled between the source electrode and the drain electrode and includes a first semiconductor layer of the first doping type, a second semiconductor layer of the first doping type, and a pn-junction arranged between the first semiconductor layer and the source electrode. The second semiconductor layer has a higher doping concentration than the first semiconductor layer and is arranged between the second semiconductor layer and the drift region. The drain electrode is electrically connected to the second semiconductor layer.

    Method of manufacturing a semiconductor device and semiconductor device
    17.
    发明授权
    Method of manufacturing a semiconductor device and semiconductor device 有权
    制造半导体器件和半导体器件的方法

    公开(公告)号：US09530884B2

    公开(公告)日：2016-12-27

    申请号：US14868909

    申请日：2015-09-29

    Applicant: Infineon Technologies AG

    Inventor： Andreas Meiser ,  Till Schloesser

    IPC: H01L29/78 ,  H01L29/40 ,  H01L29/10 ,  H01L29/417 ,  H01L21/265 ,  H01L29/66

    CPC classification number: H01L29/7825 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66696 ,  H01L29/66704 ,  H01L29/7835

    Abstract: A method of manufacturing a semiconductor device including a transistor comprises forming field plate trenches in a main surface of a semiconductor substrate, a drift zone being defined between adjacent field plate trenches, forming a field dielectric layer in the field plate trenches, thereafter, forming gate trenches in the main surface of the semiconductor substrate, a channel region being defined between adjacent gate trenches, and forming a conductive material in at least some of the field plate trenches and in at least some of the gate trenches. The method further comprising forming a source region and forming a drain region in the main surface of the semiconductor substrate.

    Abstract translation: 制造包括晶体管的半导体器件的方法包括在半导体衬底的主表面中形成场板沟槽，在相邻的场板沟槽之间限定漂移区，在场板栅沟中形成场介电层，之后形成栅极 在半导体衬底的主表面中的沟槽，沟道区域被限定在相邻栅极沟槽之间，并且在至少一些场板沟槽和至少一些栅极沟槽中形成导电材料。 该方法还包括形成源极区域并在半导体衬底的主表面中形成漏极区域。

    Method for Manufacturing a Semiconductor Device Using Tilted Ion Implantation Processes, Semiconductor Device and Integrated Circuit
    18.
    发明申请
    Method for Manufacturing a Semiconductor Device Using Tilted Ion Implantation Processes, Semiconductor Device and Integrated Circuit 有权
    使用倾斜离子注入工艺制造半导体器件的方法，半导体器件和集成电路

    公开(公告)号：US20160322357A1

    公开(公告)日：2016-11-03

    申请号：US15138739

    申请日：2016-04-26

    Applicant: Infineon Technologies AG

    Inventor： Andreas Meiser ,  Till Schloesser

    IPC: H01L27/092 ,  H01L29/08 ,  H01L29/10 ,  H05B33/08 ,  H01L21/8238 ,  H01L21/265 ,  H01L21/266 ,  H01L29/417 ,  H01L29/423

    CPC classification number: H05B33/083 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66659 ,  H01L29/78

    Abstract: A semiconductor device includes first and second field effect transistors (FETs) formed in a semiconductor substrate having a first main surface. The first FET includes first source and drain contact grooves, each running in a first direction parallel to the first main surface, each formed in the first main surface. First source regions are electrically connected to a conductive material in the first source contact groove. First drain regions are electrically connected to a conductive material in the first drain contact groove. The second FET includes second source and drain contact grooves, each running in a second direction parallel to the first main surface, each formed in the first main surface. Second source regions are electrically connected to a conductive material in the second source contact groove, and second drain regions are electrically connected to a conductive material in the second drain contact groove.

    Abstract translation: 半导体器件包括形成在具有第一主表面的半导体衬底中的第一和第二场效应晶体管（FET）。 第一FET包括第一源极和漏极接触槽，每个沿着平行于第一主表面的第一方向延伸，每个形成在第一主表面中。 第一源极区域与第一源极接触槽中的导电材料电连接。 第一漏极区电连接到第一漏极接触槽中的导电材料。 第二FET包括第二源极和漏极接触槽，每个在与第一主表面平行的第二方向上延伸，每个形成在第一主表面中。 第二源极区域与第二源极接触槽中的导电材料电连接，并且第二漏极区域电连接到第二漏极接触槽中的导电材料。

    Semiconductor Device Including a Diode at Least Partly Arranged in a Trench
    19.
    发明申请
    Semiconductor Device Including a Diode at Least Partly Arranged in a Trench 有权
    包括二极管的半导体器件至少部分安排在沟槽中

    公开(公告)号：US20160307885A1

    公开(公告)日：2016-10-20

    申请号：US15189031

    申请日：2016-06-22

    Applicant: Infineon Technologies AG

    Inventor： Joachim Weyers ,  Anton Mauder ,  Franz Hirler ,  Andreas Meiser ,  Ulrich Glaser

    IPC: H01L27/02 ,  H01L29/40 ,  H01L29/872

    CPC classification number: H01L27/0255 ,  H01L27/06 ,  H01L27/0814 ,  H01L29/407 ,  H01L29/861 ,  H01L29/8611 ,  H01L29/8725

    Abstract: A semiconductor device includes a semiconductor body including a first trench extending into the semiconductor body from a first surface and a diode including an anode region and a cathode region. One of the anode region and the cathode region is at least partly arranged in the first trench. The other one of the anode region and the cathode region includes a first semiconductor region directly adjoining the one of the anode region and the cathode region from outside of the first trench, thereby constituting a pn junction. The semiconductor device further includes a conducting path through a sidewall of the first trench.

    Abstract translation: 半导体器件包括半导体本体，其包括从第一表面延伸到半导体本体中的第一沟槽和包括阳极区域和阴极区域的二极管。 阳极区域和阴极区域中的一个至少部分地布置在第一沟槽中。 阳极区域和阴极区域中的另一个包括从第一沟槽的外部直接邻接阳极区域和阴极区域中的一个的第一半导体区域，从而构成pn结。 半导体器件还包括穿过第一沟槽的侧壁的导电路径。

    Method for Producing a Controllable Semiconductor Component Having Trenches with Different Widths and Depths
    20.
    发明申请
    Method for Producing a Controllable Semiconductor Component Having Trenches with Different Widths and Depths 有权
    制造具有不同宽度和深度的沟槽的可控半导体部件的方法

    公开(公告)号：US20160284840A1

    公开(公告)日：2016-09-29

    申请号：US15173337

    申请日：2016-06-03

    Applicant: Infineon Technologies AG

    Inventor： Andreas Meiser ,  Markus Zundel

    IPC: H01L29/78 ,  H01L29/40 ,  H01L29/10 ,  H01L29/66

    CPC classification number: H01L29/7813 ,  H01L21/28008 ,  H01L21/28229 ,  H01L21/743 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L29/1095 ,  H01L29/401 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/51 ,  H01L29/66734 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A controllable semiconductor component is produced by providing a semiconductor body with a top side and a bottom side, and forming a first trench protruding from the top side into the semiconductor body and a second trench protruding from the top side into the semiconductor body. In a common process, an oxide layer is formed in the first trench and in the second trench such that the oxide layer fills the first trench and electrically insulates a surface of the second trench. The oxide layer is removed from the first trench completely or at least partly such that the semiconductor body has an exposed first surface area arranged in the first trench. An electrically conductive material is filled into the second trench, and the semiconductor body and the oxide layer are partially removed such that the electrically conductive material has an exposed second surface area at the bottom side.

    Abstract translation: 通过提供具有顶侧和底侧的半导体本体，并且形成从顶侧突出到半导体本体中的第一沟槽和从顶侧突出到半导体本体中的第二沟槽来制造可控半导体部件。 在通常的工艺中，在第一沟槽和第二沟槽中形成氧化物层，使得氧化物层填充第一沟槽并使第二沟槽的表面电绝缘。 完全或至少部分地从第一沟槽去除氧化物层，使得半导体主体具有布置在第一沟槽中的暴露的第一表面区域。 将导电材料填充到第二沟槽中，并且半导体本体和氧化物层被部分地去除，使得导电材料在底侧具有暴露的第二表面区域。

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