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公开(公告)号：US20160380181A1
公开(公告)日：2016-12-29
申请号：US14947649
申请日：2015-11-20
Applicant: Infineon Technologies AG
Inventor： Thorsten Meyer , Martin Gruber , Rainer Markus Schaller , Franz Jost , Stefan Mieslinger , Liu Chen , Toni Salminen , Giuliano Angelo Babulano , Jens Oetjen , Markus Dinkel
CPC classification number: H01L43/02 , G01R33/07 , G01R33/09 , H01L27/22 , H01L43/065 , H01L43/08 , H01L2224/0603 , H01L2224/37147 , H01L2224/37599 , H01L2224/40 , H01L2224/48137 , H01L2224/4903 , H01L2224/49171 , H01L2224/49175 , H01L2924/00014
Abstract: A semiconductor package includes a semiconductor die attached to a substrate and a magnetic field sensor included as part of the same semiconductor package as the semiconductor die and positioned in close proximity to a current pathway of the semiconductor die so that the magnetic field sensor can sense a magnetic field produced by current flowing in the current pathway. The magnetic field sensor includes a first magnetic field sensing component galvanically isolated from the current pathway and positioned so that a magnetic field produced by current flowing in the current pathway impinges on the first magnetic field sensing component in a first direction. The magnetic field sensor also includes a second magnetic field sensing component galvanically isolated from the current pathway and positioned so that the magnetic field impinges on the second magnetic field sensing component in a second direction different than the first direction.
Abstract translation: 半导体封装包括附接到衬底的半导体管芯和作为与半导体管芯相同的半导体封装的一部分的磁场传感器，并且位于靠近半导体管芯的电流通路的位置，使得磁场传感器可感测 电流在电流通路中流动产生的磁场。 磁场传感器包括与电流通路电隔离的第一磁场感测部件，并被定位成使得在电流通路中流动的电流产生的磁场沿第一方向冲击第一磁场感测部件。 磁场传感器还包括与电流路径电隔离并定位成使得磁场在不同于第一方向的第二方向上撞击在第二磁场感测部件上的第二磁场感测部件。
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公开(公告)号：US20160379966A1
公开(公告)日：2016-12-29
申请号：US14747382
申请日：2015-06-23
Applicant: Infineon Technologies AG
Inventor： Liu Chen , Toni Salminen , Stefan Mieslinger , Giuliano Angelo Babulano , Jens Oetjen , Markus Dinkel , Franz Jost
IPC: H01L25/16 , H01L43/04 , H01L43/08 , G01R33/07 , H01L23/31 , H01L23/58 , H01L23/498 , G01R33/09 , H01L43/02 , H01L23/495
CPC classification number: H01L25/16 , G01R33/007 , G01R33/07 , G01R33/09 , H01L23/3107 , H01L23/3735 , H01L23/4952 , H01L23/49524 , H01L23/49541 , H01L23/49562 , H01L23/49575 , H01L23/49589 , H01L23/49838 , H01L23/58 , H01L23/62 , H01L43/00 , H01L43/02 , H01L43/04 , H01L43/08 , H01L2224/371 , H01L2224/37147 , H01L2224/40245 , H01L2224/48137 , H01L2224/48247 , H01L2224/4903
Abstract: A power semiconductor package includes a substrate having a plurality of metal leads, a power semiconductor die attached to a first one of the leads and a magnetic field sensor integrated in the same power semiconductor package as the power semiconductor die and positioned in close proximity to a current pathway of the power semiconductor die. The magnetic field sensor is operable to generate a signal in response to a magnetic field produced by current flowing in the current pathway, the magnitude of the signal being proportional to the amount of current flowing in the current pathway.
Abstract translation: 功率半导体封装包括具有多个金属引线的基板，附接到第一引线的功率半导体管芯和集成在与功率半导体管芯相同的功率半导体封装中并且定位成靠近 功率半导体芯片的电流通路。 磁场传感器可操作以响应于在电流通路中流动的电流产生的磁场产生信号，该信号的幅度与当前通路中流动的电流量成比例。
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公开(公告)号：US09385059B2
公开(公告)日：2016-07-05
申请号：US14011772
申请日：2013-08-28
Applicant: Infineon Technologies AG
Inventor： Peter Ossimitz , Juergen Schaefer , Liu Chen , Markus Dinkel , Stefan Macheiner
IPC: H05K7/20 , H01L23/34 , H01L21/48 , H05K3/32 , H01L23/367 , H01L23/40 , H05K3/28 , H05K5/00 , H01L23/31 , H01L23/427 , H01L23/498 , H05K1/02
CPC classification number: H01L23/34 , H01L21/4882 , H01L23/3128 , H01L23/367 , H01L23/3675 , H01L23/4006 , H01L23/4093 , H01L23/427 , H01L23/49822 , H01L2023/405 , H01L2224/16225 , H01L2924/0002 , H01L2924/13055 , H05K1/0206 , H05K1/0209 , H05K3/284 , H05K3/32 , H05K5/0034 , H05K7/20854 , H05K2201/10166 , Y10T29/49146 , H01L2924/00
Abstract: An electronic device comprises a substrate, at least one electronic chip mounted on and electrically connected to the substrate and being configured as a system control unit for controlling a connected system, a heat removal structure thermally connected to the at least one electronic chip and configured for removing heat generated by the at least one electronic chip upon operation of the electronic device, and an overmolding structure configured for at least partially encapsulating at least the at least one electronic chip and the substrate.
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公开(公告)号：US20150062825A1
公开(公告)日：2015-03-05
申请号：US14011772
申请日：2013-08-28
Applicant: Infineon Technologies AG
Inventor： Peter Ossimitz , Juergen Schaefer , Liu Chen , Markus Dinkel , Stefan MacHeiner
CPC classification number: H01L23/34 , H01L21/4882 , H01L23/3128 , H01L23/367 , H01L23/3675 , H01L23/4006 , H01L23/4093 , H01L23/427 , H01L23/49822 , H01L2023/405 , H01L2224/16225 , H01L2924/0002 , H01L2924/13055 , H05K1/0206 , H05K1/0209 , H05K3/284 , H05K3/32 , H05K5/0034 , H05K7/20854 , H05K2201/10166 , Y10T29/49146 , H01L2924/00
Abstract: An electronic device comprises a substrate, at least one electronic chip mounted on and electrically connected to the substrate and being configured as a system control unit for controlling a connected system, a heat removal structure thermally connected to the at least one electronic chip and configured for removing heat generated by the at least one electronic chip upon operation of the electronic device, and an overmolding structure configured for at least partially encapsulating at least the at least one electronic chip and the substrate.
Abstract translation: 电子设备包括基板，安装在基板上并与其电连接的至少一个电子芯片，并且被配置为用于控制连接的系统的系统控制单元，热连接到所述至少一个电子芯片的散热结构， 在电子设备操作时去除由至少一个电子芯片产生的热量，以及被配置用于至少部分地封装至少一个电子芯片和基板的二次模制结构。
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15.发明公开公开(公告)号：US20230240012A1
公开(公告)日：2023-07-27
申请号：US18122988
申请日：2023-03-17
Applicant: Infineon Technologies AG
Inventor： Petteri Palm , Martin Benisek , Liu Chen , Frank Daeche , Josef Maerz
CPC classification number: H05K1/181 , H05K1/021 , H05K1/0298 , H05K1/0306
Abstract: A power electronic assembly includes a board having metal layers laminated onto or between electrically insulating layers, and a laminate inlay embedded in the board. A first metal layer provides electrical contacts at a first side of the board. A second metal layer provides a thermal contact at a second side of the board. A third metal layer is positioned between the first metal layer and the laminate inlay and configured to distribute a load current switched by the laminate inlay. A fourth metal layer is positioned between the second metal layer and the laminate inlay and configured as a primary thermal conduction path for heat generated by the laminate inlay during switching of the load current. A first electrically insulating layer separates the fourth metal layer from the second metal layer so that the fourth metal layer is electrically isolated from but thermally connected to the second metal layer.
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Patent Agency Ranking
公开(公告)号：US11127853B2
公开(公告)日：2021-09-21
申请号：US16433889
申请日：2019-06-06
Applicant: Infineon Technologies AG
IPC: H01L29/78 , H01L29/423 , H01L27/088 , H01L29/06
Abstract: A transistor device is disclosed. The transistor device includes: a semiconductor body; a source conductor on top of the semiconductor body; a source clip on top of the source conductor and electrically connected to the source conductor; a first active device region arranged in the semiconductor body, covered by the source conductor and the source clip, and including at least one device cell; and a second active device region arranged in the semiconductor body, covered by regions of the source conductor that are not covered by the source clip, and including at least one device cell. The first active device region has a first area specific on-resistance and the second active device region has a second area specific on-resistance, the second area specific on-resistance being greater than the first area specific on-resistance.
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公开(公告)号：US10290567B2
公开(公告)日：2019-05-14
申请号：US15694086
申请日：2017-09-01
Applicant: Infineon Technologies AG
Inventor： Rainald Sander , Liu Chen , Teck Sim Lee
IPC: H01L23/49 , H01L23/495 , H01L23/00 , H01L23/31
Abstract: A package which comprises an electrically conductive chip carrier, a first chip comprising a first connection terminal, a second connection terminal located on the chip carrier and a control terminal, a second chip comprising a first connection terminal, a second connection terminal located on the chip carrier and a control terminal, wherein the first chip and the second chip are connected to form a half bridge having inlet terminals and an outlet terminal, and a clip having three connection sections connecting the second connection terminal of the first chip with the first connection terminal of the second chip and with the outlet terminal of the half bridge.
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18.发明申请公开(公告)号：US20180342438A1
公开(公告)日：2018-11-29
申请号：US15605091
申请日：2017-05-25
Applicant: Infineon Technologies AG
Inventor： Liu Chen , Teck Sim Lee , Jia Yi Wong , Wei Han Koo , Thomas Stoek , Gilles Delarozee
IPC: H01L23/367 , H01L23/492 , H01L23/495 , H01L21/56
Abstract: A semiconductor chip package includes an electrically conducting carrier and a semiconductor chip disposed over the electrically conducting carrier. The semiconductor chip has a first surface facing the electrically conducting carrier and a second surface opposite the first surface. A metal plate has a first surface mechanically connected to the second surface of the semiconductor chip and a second surface opposite the first surface of the metal plate. The metal plate completely overlaps the second surface of the semiconductor chip. The second surface of the metal plate is at least partially exposed at a periphery of the semiconductor chip package.
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公开(公告)号：US09681558B2
公开(公告)日：2017-06-13
申请号：US14457663
申请日：2014-08-12
Applicant: Infineon Technologies AG
Inventor： Liu Chen , Markus Dinkel , Toni Salminen
CPC classification number: H05K3/40 , H01L24/19 , H01L24/20 , H01L2224/04105 , H01L2224/12105 , H01L2224/16227 , H01L2224/16235 , H01L2224/18 , H01L2224/32245 , H01L2224/73267 , H01L2224/92244 , H01L2924/19105 , H05K3/0017 , H05K3/4697 , H05K7/06 , H05K2201/10166
Abstract: A integrated power module with integrated power electronic circuitry and logic circuitry includes an embedded power semiconductor module including one or more power semiconductor dies embedded in a dielectric material, a multi-layer logic printed circuit board with one or more logic dies mounted to a surface of the logic printed circuit board, and a flexible connection integrally formed between the embedded power semiconductor module and the logic printed circuit board. The flexible connection mechanically connects the embedded power semiconductor module to the logic printed circuit board and provides an electrical pathway between the embedded power semiconductor module and the logic printed circuit board. A method of manufacturing the integrated power module is also provided.
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公开(公告)号：US20160050768A1
公开(公告)日：2016-02-18
申请号：US14457663
申请日：2014-08-12
Applicant: Infineon Technologies AG
Inventor： Liu Chen , Markus Dinkel , Toni Salminen
CPC classification number: H05K3/40 , H01L24/19 , H01L24/20 , H01L2224/04105 , H01L2224/12105 , H01L2224/16227 , H01L2224/16235 , H01L2224/18 , H01L2224/32245 , H01L2224/73267 , H01L2224/92244 , H01L2924/19105 , H05K3/0017 , H05K3/4697 , H05K7/06 , H05K2201/10166
Abstract: A integrated power module with integrated power electronic circuitry and logic circuitry includes an embedded power semiconductor module including one or more power semiconductor dies embedded in a dielectric material, a multi-layer logic printed circuit board with one or more logic dies mounted to a surface of the logic printed circuit board, and a flexible connection integrally formed between the embedded power semiconductor module and the logic printed circuit board. The flexible connection mechanically connects the embedded power semiconductor module to the logic printed circuit board and provides an electrical pathway between the embedded power semiconductor module and the logic printed circuit board. A method of manufacturing the integrated power module is also provided.
Abstract translation: 具有集成功率电子电路和逻辑电路的集成电源模块包括嵌入式功率半导体模块，该嵌入式功率半导体模块包括嵌入电介质材料中的一个或多个功率半导体芯片，具有一个或多个逻辑裸片的多层逻辑印刷电路板， 逻辑印刷电路板和一体地形成在嵌入式功率半导体模块和逻辑印刷电路板之间的柔性连接。 柔性连接将嵌入式功率半导体模块机械地连接到逻辑印刷电路板，并在嵌入式功率半导体模块和逻辑印刷电路板之间提供电气通路。 还提供了一种制造集成电源模块的方法。
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