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公开(公告)号：US09564423B2
公开(公告)日：2017-02-07
申请号：US14747382
申请日：2015-06-23
Applicant: Infineon Technologies AG
Inventor： Liu Chen , Toni Salminen , Stefan Mieslinger , Giuliano Angelo Babulano , Jens Oetjen , Markus Dinkel , Franz Jost
IPC: H01L25/16 , H01L43/02 , H01L43/04 , H01L43/08 , H01L23/495 , H01L23/31 , H01L23/58 , H01L23/498 , G01R33/09 , G01R33/07
CPC classification number: H01L25/16 , G01R33/007 , G01R33/07 , G01R33/09 , H01L23/3107 , H01L23/3735 , H01L23/4952 , H01L23/49524 , H01L23/49541 , H01L23/49562 , H01L23/49575 , H01L23/49589 , H01L23/49838 , H01L23/58 , H01L23/62 , H01L43/00 , H01L43/02 , H01L43/04 , H01L43/08 , H01L2224/371 , H01L2224/37147 , H01L2224/40245 , H01L2224/48137 , H01L2224/48247 , H01L2224/4903
Abstract: A power semiconductor package includes a substrate having a plurality of metal leads, a power semiconductor die attached to a first one of the leads and a magnetic field sensor integrated in the same power semiconductor package as the power semiconductor die and positioned in close proximity to a current pathway of the power semiconductor die. The magnetic field sensor is operable to generate a signal in response to a magnetic field produced by current flowing in the current pathway, the magnitude of the signal being proportional to the amount of current flowing in the current pathway.
Abstract translation: 功率半导体封装包括具有多个金属引线的基板，附接到第一引线的功率半导体管芯和集成在与功率半导体管芯相同的功率半导体封装中并且定位成靠近 功率半导体芯片的电流通路。 磁场传感器可操作以响应于在电流通路中流动的电流产生的磁场产生信号，该信号的幅度与当前通路中流动的电流量成比例。
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公开(公告)号：US11632860B2
公开(公告)日：2023-04-18
申请号：US16663947
申请日：2019-10-25
Applicant: Infineon Technologies AG
Inventor： Petteri Palm , Martin Benisek , Liu Chen , Frank Daeche , Josef Maerz
Abstract: A power electronic assembly includes a board having metal layers laminated onto or between electrically insulating layers, and a power device embedded in the board. A first metal layer provides electrical contacts at a first side of the board. A second metal layer provides a thermal contact at a second side of the board. A third metal layer is positioned between the first metal layer and the power device and configured to distribute a load current switched by the power device. A fourth metal layer is positioned between the second metal layer and the power device and configured as a primary thermal conduction path for heat generated by the power device during switching of the load current. A first electrically insulating layer separates the fourth metal layer from the second metal layer so that the fourth metal layer is electrically isolated from but thermally connected to the second metal layer.
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公开(公告)号：US10727151B2
公开(公告)日：2020-07-28
申请号：US15605091
申请日：2017-05-25
Applicant: Infineon Technologies AG
Inventor： Liu Chen , Teck Sim Lee , Jia Yi Wong , Wei Han Koo , Thomas Stoeck , Gilles Delarozee
IPC: H01L23/367 , H01L23/492 , H01L23/495 , H01L21/56 , H01L23/433 , H01L23/31 , H01L23/36 , H01L23/498 , H01L23/373
Abstract: A semiconductor chip package includes an electrically conducting carrier and a semiconductor chip disposed over the electrically conducting carrier. The semiconductor chip has a first surface facing the electrically conducting carrier and a second surface opposite the first surface. A metal plate has a first surface mechanically connected to the second surface of the semiconductor chip and a second surface opposite the first surface of the metal plate. The metal plate completely overlaps the second surface of the semiconductor chip. The second surface of the metal plate is at least partially exposed at a periphery of the semiconductor chip package.
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公开(公告)号：US10168391B2
公开(公告)日：2019-01-01
申请号：US15049923
申请日：2016-02-22
Applicant: Infineon Technologies AG
Inventor： Giuliano Angelo Babulano , Jens Oetjen , Liu Chen , Toni Salminen , Stefan Mieslinger , Markus Dinkel , Martin Gruber , Franz Jost , Thorsten Meyer , Rainer Schaller
Abstract: An interconnect module includes a metal clip having a first end section, a second end section and a middle section extending between the first and the second end sections. The first end section is configured for external attachment to a bare semiconductor die or packaged semiconductor die attached to a carrier or to a metal region of the carrier. The second end section is configured for external attachment to a different metal region of the carrier or to a different semiconductor die or packaged semiconductor die attached to the carrier. The module further includes a magnetic field sensor secured to the metal clip. The magnetic field sensor is operable to sense a magnetic field produced by current flowing through the metal clip. The interconnect module can be used to form a direct electrical connection between components and/or metal regions of a carrier to which the module is attached.
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5.发明申请Multi-Functional Interconnect Module and Carrier with Multi-Functional Interconnect Module Attached Thereto 审中-公开多功能互连模块和附加多功能互连模块的载波公开(公告)号：US20160377689A1
公开(公告)日：2016-12-29
申请号：US15049923
申请日：2016-02-22
Applicant: Infineon Technologies AG
Inventor： Giuliano Angelo Babulano , Jens Oetjen , Liu Chen , Toni Salminen , Stefan Mieslinger , Markus Dinkel , Martin Gruber , Franz Jost , Thorsten Meyer , Rainer Schaller
CPC classification number: G01R33/0047 , G01R33/091 , H01L43/02 , H01L43/08 , H01L2224/371 , H01L2224/37147 , H01L2224/40245 , H01L2224/48247 , H01L2224/4903
Abstract: An interconnect module includes a metal clip having a first end section, a second end section and a middle section extending between the first and the second end sections. The first end section is configured for external attachment to a bare semiconductor die or packaged semiconductor die attached to a carrier or to a metal region of the carrier. The second end section is configured for external attachment to a different metal region of the carrier or to a different semiconductor die or packaged semiconductor die attached to the carrier. The module further includes a magnetic field sensor secured to the metal clip. The magnetic field sensor is operable to sense a magnetic field produced by current flowing through the metal clip. The interconnect module can be used to form a direct electrical connection between components and/or metal regions of a carrier to which the module is attached.
Abstract translation: 互连模块包括具有第一端部分，第二端部部分和在第一和第二端部部分之间延伸的中间部分的金属夹。 第一端部部分被配置为外部连接到附接到载体或载体的金属区域的裸半导体管芯或封装的半导体管芯。 第二端部构造成用于外部附接到载体的不同金属区域或者附接到载体的不同的半导体管芯或封装的半导体管芯。 该模块还包括固定到金属夹的磁场传感器。 磁场传感器可操作以感测由流过金属夹的电流产生的磁场。 互连模块可以用于在模块附接到的载体的部件和/或金属区域之间形成直接电连接。
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Patent Agency Ranking
公开(公告)号：US11903132B2
公开(公告)日：2024-02-13
申请号：US18122988
申请日：2023-03-17
Applicant: Infineon Technologies AG
Inventor： Petteri Palm , Martin Benisek , Liu Chen , Frank Daeche , Josef Maerz
CPC classification number: H05K1/181 , H05K1/021 , H05K1/0298 , H05K1/0306
Abstract: A power electronic assembly includes a board having metal layers laminated onto or between electrically insulating layers, and a laminate inlay embedded in the board. A first metal layer provides electrical contacts at a first side of the board. A second metal layer provides a thermal contact at a second side of the board. A third metal layer is positioned between the first metal layer and the laminate inlay and configured to distribute a load current switched by the laminate inlay. A fourth metal layer is positioned between the second metal layer and the laminate inlay and configured as a primary thermal conduction path for heat generated by the laminate inlay during switching of the load current. A first electrically insulating layer separates the fourth metal layer from the second metal layer so that the fourth metal layer is electrically isolated from but thermally connected to the second metal layer.
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公开(公告)号：US11239127B2
公开(公告)日：2022-02-01
申请号：US16906617
申请日：2020-06-19
Applicant: Infineon Technologies AG
Inventor： Edward Myers , Liu Chen , Chee Chiew Chong , Wee Aun Jason Lim , Wee Boon Tay
Abstract: A molded semiconductor package arrangement may comprise a die pad configured to support a semiconductor; a set of leads; and a mold structure that is formed to enclose the semiconductor and the die pad within the mold structure. The set of leads and the die pad may be formed from a same piece of conductive material. An electrical contact plane of the set of leads may be offset from a bottom surface of the die pad. The mold structure may include a molded standoff that is beneath the die pad. A bottom surface of the molded standoff may extend below the electrical contact plane of the set of leads by a threshold distance that corresponds to a thickness of the molded standoff.
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公开(公告)号：US20210127490A1
公开(公告)日：2021-04-29
申请号：US16663947
申请日：2019-10-25
Applicant: Infineon Technologies AG
Inventor： Petteri Palm , Martin Benisek , Liu Chen , Frank Daeche , Josef Maerz
Abstract: A power electronic assembly includes a board having metal layers laminated onto or between electrically insulating layers, and a power device embedded in the board. A first metal layer provides electrical contacts at a first side of the board. A second metal layer provides a thermal contact at a second side of the board. A third metal layer is positioned between the first metal layer and the power device and configured to distribute a load current switched by the power device. A fourth metal layer is positioned between the second metal layer and the power device and configured as a primary thermal conduction path for heat generated by the power device during switching of the load current. A first electrically insulating layer separates the fourth metal layer from the second metal layer so that the fourth metal layer is electrically isolated from but thermally connected to the second metal layer.
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公开(公告)号：US20190386133A1
公开(公告)日：2019-12-19
申请号：US16433889
申请日：2019-06-06
Applicant: Infineon Technologies AG
IPC: H01L29/78 , H01L29/06 , H01L27/088 , H01L29/423
Abstract: A transistor device is disclosed. The transistor device includes: a semiconductor body; a source conductor on top of the semiconductor body; a source clip on top of the source conductor and electrically connected to the source conductor; a first active device region arranged in the semiconductor body, covered by the source conductor and the source clip, and including at least one device cell; and a second active device region arranged in the semiconductor body, covered by regions of the source conductor that are not covered by the source clip, and including at least one device cell. The first active device region has a first area specific on-resistance and the second active device region has a second area specific on-resistance, the second area specific on-resistance being greater than the first area specific on-resistance.
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公开(公告)号：US09564578B2
公开(公告)日：2017-02-07
申请号：US14947649
申请日：2015-11-20
Applicant: Infineon Technologies AG
Inventor： Thorsten Meyer , Martin Gruber , Rainer Markus Schaller , Franz Jost , Stefan Mieslinger , Liu Chen , Toni Salminen , Giuliano Angelo Babulano , Jens Oetjen , Markus Dinkel
CPC classification number: H01L43/02 , G01R33/07 , G01R33/09 , H01L27/22 , H01L43/065 , H01L43/08 , H01L2224/0603 , H01L2224/37147 , H01L2224/37599 , H01L2224/40 , H01L2224/48137 , H01L2224/4903 , H01L2224/49171 , H01L2224/49175 , H01L2924/00014
Abstract: A semiconductor package includes a semiconductor die attached to a substrate and a magnetic field sensor included as part of the same semiconductor package as the semiconductor die and positioned in close proximity to a current pathway of the semiconductor die so that the magnetic field sensor can sense a magnetic field produced by current flowing in the current pathway. The magnetic field sensor includes a first magnetic field sensing component galvanically isolated from the current pathway and positioned so that a magnetic field produced by current flowing in the current pathway impinges on the first magnetic field sensing component in a first direction. The magnetic field sensor also includes a second magnetic field sensing component galvanically isolated from the current pathway and positioned so that the magnetic field impinges on the second magnetic field sensing component in a second direction different than the first direction.
Abstract translation: 半导体封装包括附接到衬底的半导体管芯和作为与半导体管芯相同的半导体封装的一部分的磁场传感器，并且位于靠近半导体管芯的电流通路的位置，使得磁场传感器可感测 电流在电流通路中流动产生的磁场。 磁场传感器包括与电流通路电隔离的第一磁场感测部件，并被定位成使得在电流通路中流动的电流产生的磁场沿第一方向冲击第一磁场感测部件。 磁场传感器还包括与电流路径电隔离并定位成使得磁场在不同于第一方向的第二方向上撞击在第二磁场感测部件上的第二磁场感测部件。
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