公开(公告)号：US20180096966A1

公开(公告)日：2018-04-05

申请号：US15284580

申请日：2016-10-04

Applicant: Infineon Technologies AG

Inventor： Thorsten Meyer ,  Gerald Ofner ,  Peter Scherl ,  Stephan Bradl ,  Stefan Miethaner ,  Alexander Heinrich ,  Horst Theuss

IPC: H01L23/00 ,  H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78

Abstract: A method of producing packaged semiconductor devices includes providing a first packaging substrate panel. A second packaging substrate panel is provided. The first and second packaging substrate panels are moved through an assembly line that includes a plurality of package assembly tools using a control mechanism. First type packaged semiconductor devices are formed on the first packaging substrate panel and second type packaged semiconductor devices are formed on the second packaging substrate panel. The second type packaged semiconductor device is different than the first type packaged semiconductor device. The control mechanism moves both of the first and packaging substrate panels through the assembly line in a non-linear manner.

公开(公告)号：US09837530B2

公开(公告)日：2017-12-05

申请号：US14868857

申请日：2015-09-29

Applicant: Infineon Technologies AG

Inventor： Stefan Decker ,  Sven Lanzerstorfer ,  Thorsten Meyer ,  Robert Zink

IPC: H01L29/00 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/10 ,  H01L29/40 ,  H01L29/739 ,  H01L29/417

CPC classification number: H01L29/7813 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7811

Abstract: A semiconductor device comprises a semiconductor body. The semiconductor body comprises insulated gate field effect transistor cells. At least one of the insulated gate field effect transistor cells comprises a source zone of a first conductivity type, a body zone of a second, complementary conductivity type, a drift zone of the first conductivity type, and a trench gate structure extending into the semiconductor body through the body zone along a vertical direction. The trench gate structure comprises a gate electrode separated from the semiconductor body by a trench dielectric. The trench dielectric comprises a source dielectric part interposed between the gate electrode and the source zone and a gate dielectric part interposed between the gate electrode and the body zone. The ratio of a maximum thickness of the source dielectric part along a lateral direction and the minimum thickness of the gate dielectric part along the lateral direction is at least 1.5.

公开(公告)号：US09461164B2

公开(公告)日：2016-10-04

申请号：US14027683

申请日：2013-09-16

Applicant: Infineon Technologies AG

Inventor： Thorsten Meyer ,  Werner Schwetlick

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/40

CPC classification number: H01L21/823487 ,  H01L21/28008 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/7851

Abstract: A semiconductor device includes a semiconductor body having a first surface and a second surface opposite to the first surface. The semiconductor device further includes first and second trenches extending from the first surface into the semiconductor body. The semiconductor device further includes at least one lateral IGFET including a first load terminal at the first surface, a second load terminal at the first surface and a gate electrode within the first trenches. The semiconductor device further includes at least one vertical IGFET including a first load terminal at the first surface, a second load terminal at the second surface and a gate electrode within the second trenches.

Abstract translation: 半导体器件包括具有第一表面和与第一表面相对的第二表面的半导体本体。 半导体器件还包括从第一表面延伸到半导体本体的第一和第二沟槽。 半导体器件还包括至少一个横向IGFET，其包括第一表面处的第一负载端子，第一表面处的第二负载端子和第一沟槽内的栅电极。 半导体器件还包括至少一个垂直IGFET，其包括第一表面处的第一负载端子，第二表面处的第二负载端子和第二沟槽内的栅电极。

公开(公告)号：US20160268397A1

公开(公告)日：2016-09-15

申请号：US15160525

申请日：2016-05-20

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Till Schloesser ,  Thorsten Meyer

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H01L21/28 ,  H01L21/76

CPC classification number: H01L29/66704 ,  H01L21/28008 ,  H01L21/76 ,  H01L21/761 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/404 ,  H01L29/407 ,  H01L29/66659 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7835

Abstract: A method of manufacturing a semiconductor device includes forming a transistor in a semiconductor substrate having a first main surface. The transistor is formed by forming a source region, forming a drain region, forming a channel region, forming a drift zone, and forming a gate electrode adjacent to at least two sides of the channel region. The channel region and the drift zone are disposed along a first direction parallel to the first main surface, between the source region and the drain region. Forming the semiconductor device further includes forming a conductive layer, a portion of the conductive layer being disposed beneath the gate electrode and insulated from the gate electrode.

公开(公告)号：US20160260803A1

公开(公告)日：2016-09-08

申请号：US15157448

申请日：2016-05-18

Applicant: Infineon Technologies AG

Inventor： Thorsten Meyer ,  Stefan Decker ,  Norbert Krischke ,  Christoph Kadow

IPC: H01L29/10 ,  H01L27/088 ,  H01L29/423 ,  H01L21/8234

CPC classification number: H01L29/105 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/823412 ,  H01L21/823807 ,  H01L27/088 ,  H01L29/4236 ,  H01L29/66537 ,  H01L29/78

Abstract: An integrated circuit having field effect transistors and manufacturing method. One embodiment provides an integrated circuit including a first FET and a second FET. At least one of source, drain, gate of the first FET is electrically connected to the corresponding one of source, drain, gate of the second FET. At least one further of source, drain, gate of the first FET and the corresponding one further of source, drain, gate of the second FET are connected to a circuit element, respectively. A dopant concentration of a body along a channel of each of the first and second FETs has a peak at a peak location within the channel.

Abstract translation: 一种具有场效应晶体管和制造方法的集成电路。 一个实施例提供了包括第一FET和第二FET的集成电路。 第一FET的源极，漏极，栅极中的至少一个电连接到第二FET的源极，漏极，栅极中的相应一个栅极。 第一FET的源极，漏极，栅极以及第二FET的源极，漏极，栅极之间的至少另外的栅极分别连接到电路元件。 沿着第一和第二FET中的每一个的通道的主体的掺杂剂浓度在通道内的峰值位置处具有峰值。

公开(公告)号：US09349834B2

公开(公告)日：2016-05-24

申请号：US14794898

申请日：2015-07-09

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Till Schloesser ,  Thorsten Meyer

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28

CPC classification number: H01L29/66704 ,  H01L21/28008 ,  H01L21/76 ,  H01L21/761 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/404 ,  H01L29/407 ,  H01L29/66659 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7835

Abstract: A method of manufacturing a semiconductor device includes forming a transistor in a semiconductor substrate having a first main surface. The transistor is formed by forming a source region, forming a drain region, forming a channel region, forming a drift zone, and forming a gate electrode adjacent to at least two sides of the channel region. The channel region and the drift zone are disposed along a first direction parallel to the first main surface, between the source region and the drain region. Forming the semiconductor device further includes forming a conductive layer, a portion of the conductive layer being disposed beneath the gate electrode and insulated from the gate electrode.

Abstract translation: 制造半导体器件的方法包括在具有第一主表面的半导体衬底中形成晶体管。 晶体管通过形成源极区域，形成漏极区域，形成沟道区域，形成漂移区域以及形成与沟道区域的至少两侧相邻的栅电极而形成。 沟道区域和漂移区沿着平行于第一主表面的第一方向，在源极区域和漏极区域之间设置。 形成半导体器件还包括形成导电层，导电层的一部分设置在栅电极下方并与栅电极绝缘。

公开(公告)号：US20150311317A1

公开(公告)日：2015-10-29

申请号：US14794898

申请日：2015-07-09

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Till Schloesser ,  Thorsten Meyer

IPC: H01L29/66 ,  H01L21/28

CPC classification number: H01L29/66704 ,  H01L21/28008 ,  H01L21/76 ,  H01L21/761 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/404 ,  H01L29/407 ,  H01L29/66659 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7835

Abstract: A method of manufacturing a semiconductor device includes forming a transistor in a semiconductor substrate having a first main surface. The transistor is formed by forming a source region, forming a drain region, forming a channel region, forming a drift zone, and forming a gate electrode adjacent to at least two sides of the channel region. The channel region and the drift zone are disposed along a first direction parallel to the first main surface, between the source region and the drain region. Forming the semiconductor device further includes forming a conductive layer, a portion of the conductive layer being disposed beneath the gate electrode and insulated from the gate electrode.

Abstract translation: 制造半导体器件的方法包括在具有第一主表面的半导体衬底中形成晶体管。 晶体管通过形成源极区域，形成漏极区域，形成沟道区域，形成漂移区域以及形成与沟道区域的至少两侧相邻的栅电极而形成。 沟道区域和漂移区沿着平行于第一主表面的第一方向，在源极区域和漏极区域之间设置。 形成半导体器件还包括形成导电层，导电层的一部分设置在栅电极下方并与栅电极绝缘。

公开(公告)号：US09064787B2

公开(公告)日：2015-06-23

申请号：US13868191

申请日：2013-04-23

Applicant: Infineon Technologies AG

Inventor： Josef Boeck ,  Rudolf Lachner ,  Maciej Wojnowski ,  Thorsten Meyer

IPC: H05K1/18 ,  H01L23/00 ,  H01L23/498 ,  H01L23/66 ,  H01Q1/44 ,  H01Q17/00 ,  H01Q23/00 ,  G01S7/03 ,  H05K3/34

CPC classification number: H01L24/20 ,  G01S7/032 ,  H01L23/49816 ,  H01L23/66 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/19 ,  H01L24/32 ,  H01L24/81 ,  H01L24/96 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/11318 ,  H01L2224/1132 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/1319 ,  H01L2224/13191 ,  H01L2224/13299 ,  H01L2224/14051 ,  H01L2224/141 ,  H01L2224/14505 ,  H01L2224/14517 ,  H01L2224/16225 ,  H01L2224/17517 ,  H01L2224/21 ,  H01L2224/2101 ,  H01L2224/211 ,  H01L2224/215 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/831 ,  H01L2924/01029 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3512 ,  H01L2924/384 ,  H01Q1/44 ,  H01Q17/00 ,  H01Q23/00 ,  H05K3/3436 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor module having one or more integrated antennas in a single package is provided herein. The semiconductor module has a bonding interconnect structure that connects an integrated package to a printed circuit board (PCB), wherein the integrated antenna structures are located at greater center-to-center distance from the IC device than the three dimensional interconnect structures. Therefore, the bonding interconnect structures are confined to a connection area that causes a part of the package containing the one or more antenna structures to extend beyond the bonding interconnect structure as a cantilevered structure. Such a bonding interconnect structure result in a package that is in contact with a PCB at a relatively small area that supports the load of the package.

Abstract translation: 本文提供了在单个封装中具有一个或多个集成天线的半导体模块。 半导体模块具有将集成封装连接到印刷电路板（PCB）的接合互连结构，其中集成天线结构位于距离IC器件比三维互连结构更大的中心到中心距离处。 因此，接合互连结构被限制在连接区域上，该连接区域使得包含一个或多个天线结构的封装的一部分延伸超过作为悬臂结构的接合互连结构。 这种接合互连结构导致在支撑封装负载的较小区域处与PCB接触的封装。

公开(公告)号：US20130241059A1

公开(公告)日：2013-09-19

申请号：US13868191

申请日：2013-04-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Josef Boeck ,  Rudolf Lachner ,  Maciej Wojnowski ,  Thorsten Meyer

IPC: H01L23/00

CPC classification number: H01L24/20 ,  G01S7/032 ,  H01L23/49816 ,  H01L23/66 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/19 ,  H01L24/32 ,  H01L24/81 ,  H01L24/96 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/11318 ,  H01L2224/1132 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/1319 ,  H01L2224/13191 ,  H01L2224/13299 ,  H01L2224/14051 ,  H01L2224/141 ,  H01L2224/14505 ,  H01L2224/14517 ,  H01L2224/16225 ,  H01L2224/17517 ,  H01L2224/21 ,  H01L2224/2101 ,  H01L2224/211 ,  H01L2224/215 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/831 ,  H01L2924/01029 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3512 ,  H01L2924/384 ,  H01Q1/44 ,  H01Q17/00 ,  H01Q23/00 ,  H05K3/3436 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor module having one or more integrated antennas in a single package is provided herein. The semiconductor module has a bonding interconnect structure that connects an integrated package to a printed circuit board (PCB), wherein the integrated antenna structures are located at greater center-to-center distance from the IC device than the three dimensional interconnect structures. Therefore, the bonding interconnect structures are confined to a connection area that causes a part of the package containing the one or more antenna structures to extend beyond the bonding interconnect structure as a cantilevered structure. Such a bonding interconnect structure result in a package that is in contact with a PCB at a relatively small area that supports the load of the package.

Abstract translation: 本文提供了在单个封装中具有一个或多个集成天线的半导体模块。 半导体模块具有将集成封装连接到印刷电路板（PCB）的接合互连结构，其中集成天线结构位于距离IC器件比三维互连结构更大的中心到中心距离处。 因此，接合互连结构被限制在连接区域上，该连接区域使得包含一个或多个天线结构的封装的一部分延伸超过作为悬臂结构的接合互连结构。 这种接合互连结构导致在支撑封装负载的较小区域处与PCB接触的封装。

公开(公告)号：US20130224921A1

公开(公告)日：2013-08-29

申请号：US13803291

申请日：2013-03-14

Applicant: Infineon Technologies AG

Inventor： Franz Hirler ,  Uwe Wahl ,  Thorsten Meyer ,  Michael Rüb ,  Armin Willmeroth ,  Markus Schmitt ,  Carolin Tolksdorf ,  Carsten Schaeffer

IPC: H01L29/66

CPC classification number: H01L29/66689 ,  H01L21/26586 ,  H01L29/0696 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66666 ,  H01L29/66704 ,  H01L29/78 ,  H01L29/7825

Abstract: A method for production of doped semiconductor regions in a semiconductor body of a lateral trench transistor includes forming a trench in the semiconductor body and introducing dopants into at least one area of the semiconductor body that is adjacent to the trench, by carrying out a process in which dopants enter the at least one area through inner walls of the trench.

Abstract translation: 在横向沟槽晶体管的半导体本体中制造掺杂半导体区域的方法包括：在半导体本体中形成沟槽，并且通过在半导体本体中进行工艺，将掺杂物引入与沟槽相邻的半导体本体的至少一个区域中 所述掺杂剂通过沟槽的内壁进入至少一个区域。