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公开(公告)号：US12293462B2
公开(公告)日：2025-05-06
申请号：US18409753
申请日：2024-01-10
Applicant: Intel Corporation
Inventor： Subramaniam Maiyuran , Saurabh Sharma , Jorge F. Garcia Pabon , Raghavendra Kamath Miyar , Sudheendra Srivathsa , Justin Decell , Aditya Navale
Abstract: An apparatus to facilitate graphics rendering is disclosed. The apparatus comprises sequencer hardware to operate in a tile mode to render objects, including performing batch formation to generate one or more batches of received objects, performing tile sequencing for each of the objects to compute tile fill intersects for each of the objects and performing a play sequencing of each of the objects.
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公开(公告)号：US20240185527A1
公开(公告)日：2024-06-06
申请号：US18409753
申请日：2024-01-10
Applicant: Intel Corporation
Inventor： Subramaniam Maiyuran , Saurabh Sharma , Jorge F. Garcia Pabon , Raghavendra Kamath Miyar , Sudheendra Srivathsa , Justin Decell , Aditya Navale
CPC classification number: G06T17/20 , G06T1/20 , G06T15/005
Abstract: An apparatus to facilitate graphics rendering is disclosed. The apparatus comprises sequencer hardware to operate in a tile mode to render objects, including performing batch formation to generate one or more batches of received objects, performing tile sequencing for each of the objects to compute tile fill intersects for each of the objects and performing a play sequencing of each of the objects.
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公开(公告)号：US11494867B2
公开(公告)日：2022-11-08
申请号：US17115555
申请日：2020-12-08
Applicant: Intel Corporation
Inventor： Saurabh Sharma , Michael Apodaca , Aditya Navale , Travis Schluessler , Vamsee Vardhan Chivukula , Abhishek Venkatesh , Subramaniam Maiyuran
IPC: G06T1/20
Abstract: An apparatus to facilitate asynchronous execution at a processing unit. The apparatus includes one or more processors to detect independent task passes that may be executed out of order in a pipeline of the processing unit, schedule a first set of processing tasks to be executed at a first set of processing elements at the processing unit and schedule a second set of tasks to be executed at a second set of processing elements, wherein execution of the first set of tasks at the first set of processing elements is to be performed simultaneous and in parallel to execution of the second set of tasks at the second set of processing elements.
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公开(公告)号：US11385952B2
公开(公告)日：2022-07-12
申请号：US17171790
申请日：2021-02-09
Applicant: Intel Corporation
Inventor： Balaji Vembu , Bryan White , Ankur Shah , Murali Ramadoss , David Puffer , Altug Koker , Aditya Navale , Mahesh Natu
Abstract: Apparatus and method for scalable error reporting. For example, one embodiment of an apparatus comprises error detection circuitry to detect an error in a component of a first tile within a tile-based hierarchy of a processing device; error classification circuitry to classify the error and record first error data based on the classification; a first tile interface to combine the first error data with second error data received from one or more other components associated with the first tile to generate first accumulated error data; and a master tile interface to combine the first accumulated error data with second accumulated error data received from at least one other tile interface to generate second accumulated error data and to provide the second accumulated error data to a host executing an application to process the second accumulated error data.
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公开(公告)号：US11288191B1
公开(公告)日：2022-03-29
申请号：US17132147
申请日：2020-12-23
Applicant: Intel Corporation
Inventor： Hema Chand Nalluri , Aditya Navale , Altug Koker , Brandon Fliflet , Jeffery S. Boles , James Valerio , Vasanth Ranganathan , Anirban Kundu , Pattabhiraman K
IPC: G06F12/0802
Abstract: An apparatus to facilitate memory flushing is disclosed. The apparatus comprises a cache memory, one or more processing resources, tracker hardware to dispatch workloads for execution at the processing resources and to monitor the workloads to track completion of the execution, range based flush (RBF) hardware to process RBF commands and generate a flush indication to flush data from the cache memory and a flush controller to receive the flush indication and perform a flush operation to discard data from the cache memory at an address range provided in the flush indication.
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Patent Agency Ranking
公开(公告)号：US11250627B2
公开(公告)日：2022-02-15
申请号：US16914783
申请日：2020-06-29
Applicant: Intel Corporation
Inventor： Subramaniam Maiyuran , Saurabh Sharma , Jorge F. Garcia Pabon , Raghavendra Kamath Miyar , Sudheendra Srivathsa , Justin Decell , Aditya Navale
Abstract: An apparatus to facilitate graphics rendering is disclosed. The apparatus comprises sequencer hardware to operate in a tile mode to render objects, including performing batch formation to generate one or more batches of received objects, performing tile sequencing for each of the objects to compute tile fill intersects for each of the objects and performing a play sequencing of each of the objects.
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17.发明授权公开(公告)号：US10796472B2
公开(公告)日：2020-10-06
申请号：US16024821
申请日：2018-06-30
Applicant: Intel Corporation
Inventor： Michael Apodaca , Ankur Shah , Ben Ashbaugh , Brandon Fliflet , Hema Nalluri , Pattabhiraman K , Peter Doyle , Joseph Koston , James Valerio , Murali Ramadoss , Altug Koker , Aditya Navale , Prasoonkumar Surti , Balaji Vembu
IPC: G06T15/00
Abstract: Apparatus and method for simultaneous command streamers. For example, one embodiment of an apparatus comprises: a plurality of work element queues to store work elements for a plurality of thread contexts, each work element associated with a context descriptor identifying a context storage region in memory; a plurality of command streamers, each command streamer associated with one of the plurality of work element queues, the command streamers to independently submit instructions for execution as specified by the work elements; a thread dispatcher to evaluate the thread contexts including priority values, to tag each instruction with an execution identifier (ID), and to responsively dispatch each instruction including the execution ID in accordance with the thread context; and a plurality of graphics functional units to independently execute each instruction dispatched by the thread dispatcher and to associate each instruction with a thread context based on its execution ID.
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公开(公告)号：US10769751B2
公开(公告)日：2020-09-08
申请号：US16543849
申请日：2019-08-19
Applicant: Intel Corporation
Inventor： Subramaniam Maiyuran , Jorge F. Garcia Pabon , Vikranth Vemulapalli , Chandra S. Gurram , Aditya Navale , Saurabh Sharma
Abstract: A processing apparatus is described. The apparatus includes a graphics processing unit (GPU), including a register file having a plurality of channels to store data and an execution unit to examine data at each of the plurality of channels, read a data value from a first of the plurality of channels upon a determination that each of the plurality of channels has the same data and execute a single input multi data (SIMD) instruction based on the data value.
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公开(公告)号：US10579382B2
公开(公告)日：2020-03-03
申请号：US15879416
申请日：2018-01-24
Applicant: Intel Corporation
Inventor： Rajesh Sankaran , Ankur Shah , Bryan White , Hema Nalluri , David Puffer , Murali Ramadoss , Altug Koker , Aditya Navale , Balaji Vembu
IPC: G06F9/30 , G06F9/32 , G06T1/20 , G06F12/1009
Abstract: An apparatus and method for scalable interrupt reporting. For example, one embodiment of an apparatus comprises: a host processor to execute one or more processes having a corresponding one or more process contexts associated therewith; and a graphics processing engine to, upon initiating execution of a first process, determine a current process context associated with the first process including a first pointer to a first system memory region to store an interrupt status, a second pointer to a second system memory region to store interrupt enable and/or interrupt mask data for one or more interrupt events, and address/data values associated with a message signaled interrupt (MSI); the graphics processing engine, in response to an interrupt event, to evaluate the interrupt enable data from the second system memory region to determine whether the interrupt event is enabled, to report the interrupt event, if enabled, by writing a specified value to the first system memory region identified by the first pointer, and to generate a first MSI corresponding to the interrupt event by writing the MSI address/data values to an output accessible by the host processor.
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公开(公告)号：US09928564B2
公开(公告)日：2018-03-27
申请号：US14315597
申请日：2014-06-26
Applicant: Intel Corporation
Inventor： Prasoonkumar Surti , Aditya Navale , Jeffery S. Boles
CPC classification number: G06T1/20 , G06T15/005 , G09G5/363 , G09G2360/08
Abstract: Systems and methods may provide for receiving a plurality of signals from a software module associated with a shared resource such as, for example, an unordered access view (UAV). The plurality of signals may include a first signal that indicates whether a draw call accesses the shared resource, a second signal that indicates whether a boundary of the draw call has been reached, and a third signal that indicates whether the draw call has a coherency requirement. Additionally, a workload corresponding to the draw call may be selectively dispatched in a shader invocation based on the plurality of signals.
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