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公开(公告)号：US20240095201A1
公开(公告)日：2024-03-21
申请号：US18459311
申请日：2023-08-31
Applicant: Intel Corporation
Inventor： David Puffer , Ankur Shah , Niranjan Cooray , Bryan White , Balaji Vembu , Hema Chand Nalluri , Kritika Bala
CPC classification number: G06F13/24 , G06F13/1668 , G06T1/20
Abstract: Embodiments described herein provide techniques to facilitate scalable interrupts and workload submission for a virtualized graphics processor. The techniques include memory-based interrupt reporting and shared work queue submission for multiple software domains.
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公开(公告)号：US11704181B2
公开(公告)日：2023-07-18
申请号：US17849356
申请日：2022-06-24
Applicant: Intel Corporation
Inventor： Balaji Vembu , Bryan White , Ankur Shah , Murali Ramadoss , David Puffer , Altug Koker , Aditya Navale , Mahesh Natu
CPC classification number: G06F11/0769 , G06F11/0784 , G06F11/0787
Abstract: Apparatus and method for scalable error reporting. For example, one embodiment of an apparatus comprises error detection circuitry to detect an error in a component of a first tile within a tile-based hierarchy of a processing device; error classification circuitry to classify the error and record first error data based on the classification; a first tile interface to combine the first error data with second error data received from one or more other components associated with the first tile to generate first accumulated error data; and a master tile interface to combine the first accumulated error data with second accumulated error data received from at least one other tile interface to generate second accumulated error data and to provide the second accumulated error data to a host executing an application to process the second accumulated error data.
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公开(公告)号：US12197358B2
公开(公告)日：2025-01-14
申请号：US18459311
申请日：2023-08-31
Applicant: Intel Corporation
Inventor： David Puffer , Ankur Shah , Niranjan Cooray , Bryan White , Balaji Vembu , Hema Chand Nalluri , Kritika Bala
Abstract: Embodiments described herein provide techniques to facilitate scalable interrupts and workload submission for a virtualized graphics processor. The techniques include memory-based interrupt reporting and shared work queue submission for multiple software domains.
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公开(公告)号：US10922161B2
公开(公告)日：2021-02-16
申请号：US16203578
申请日：2018-11-28
Applicant: Intel Corporation
Inventor： Balaji Vembu , Bryan White , Ankur Shah , Murali Ramadoss , David Puffer , Altug Koker , Aditya Navale , Mahesh Natu
Abstract: Apparatus and method for scalable error reporting. For example, one embodiment of an apparatus comprises error detection circuitry to detect an error in a component of a first tile within a tile-based hierarchy of a processing device; error classification circuitry to classify the error and record first error data based on the classification; a first tile interface to combine the first error data with second error data received from one or more other components associated with the first tile to generate first accumulated error data; and a master tile interface to combine the first accumulated error data with second accumulated error data received from at least one other tile interface to generate second accumulated error data and to provide the second accumulated error data to a host executing an application to process the second accumulated error data.
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公开(公告)号：US11385952B2
公开(公告)日：2022-07-12
申请号：US17171790
申请日：2021-02-09
Applicant: Intel Corporation
Inventor： Balaji Vembu , Bryan White , Ankur Shah , Murali Ramadoss , David Puffer , Altug Koker , Aditya Navale , Mahesh Natu
Abstract: Apparatus and method for scalable error reporting. For example, one embodiment of an apparatus comprises error detection circuitry to detect an error in a component of a first tile within a tile-based hierarchy of a processing device; error classification circuitry to classify the error and record first error data based on the classification; a first tile interface to combine the first error data with second error data received from one or more other components associated with the first tile to generate first accumulated error data; and a master tile interface to combine the first accumulated error data with second accumulated error data received from at least one other tile interface to generate second accumulated error data and to provide the second accumulated error data to a host executing an application to process the second accumulated error data.
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Patent Agency Ranking
公开(公告)号：US10579382B2
公开(公告)日：2020-03-03
申请号：US15879416
申请日：2018-01-24
Applicant: Intel Corporation
Inventor： Rajesh Sankaran , Ankur Shah , Bryan White , Hema Nalluri , David Puffer , Murali Ramadoss , Altug Koker , Aditya Navale , Balaji Vembu
IPC: G06F9/30 , G06F9/32 , G06T1/20 , G06F12/1009
Abstract: An apparatus and method for scalable interrupt reporting. For example, one embodiment of an apparatus comprises: a host processor to execute one or more processes having a corresponding one or more process contexts associated therewith; and a graphics processing engine to, upon initiating execution of a first process, determine a current process context associated with the first process including a first pointer to a first system memory region to store an interrupt status, a second pointer to a second system memory region to store interrupt enable and/or interrupt mask data for one or more interrupt events, and address/data values associated with a message signaled interrupt (MSI); the graphics processing engine, in response to an interrupt event, to evaluate the interrupt enable data from the second system memory region to determine whether the interrupt event is enabled, to report the interrupt event, if enabled, by writing a specified value to the first system memory region identified by the first pointer, and to generate a first MSI corresponding to the interrupt event by writing the MSI address/data values to an output accessible by the host processor.
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公开(公告)号：US20230297526A1
公开(公告)日：2023-09-21
申请号：US17832305
申请日：2022-06-03
Applicant: Intel Corporation
Inventor： David Puffer , Ankur Shah , Niranjan Cooray , Bryan White , Balaji Vembu , Hema Chand Nalluri , Kritika Bala
CPC classification number: G06F13/24 , G06F13/1668 , G06T1/20
Abstract: Embodiments described herein provide techniques to facilitate scalable interrupts and workload submission for a virtualized graphics processor. The techniques include memory-based interrupt reporting and shared work queue submission for multiple software domains.
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公开(公告)号：US11748283B1
公开(公告)日：2023-09-05
申请号：US17832305
申请日：2022-06-03
Applicant: Intel Corporation
Inventor： David Puffer , Ankur Shah , Niranjan Cooray , Bryan White , Balaji Vembu , Hema Chand Nalluri , Kritika Bala
IPC: G06F9/48 , G06F12/084 , G06F13/24 , G06F13/16 , G06T1/20
CPC classification number: G06F13/24 , G06F13/1668 , G06T1/20
Abstract: Embodiments described herein provide techniques to facilitate scalable interrupts and workload submission for a virtualized graphics processor. The techniques include memory-based interrupt reporting and shared work queue submission for multiple software domains.
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公开(公告)号：US20220222340A1
公开(公告)日：2022-07-14
申请号：US17711883
申请日：2022-04-01
Applicant: Intel Corporation
Inventor： Vidhya Krishnan , Ankur Shah , Bryan White , Daniel Nemiroff , David Puffer , Julien Carreno , Scott Janus , Ravi Sahita , Hema Nalluri , Utkarsh Y. Kakaiya
Abstract: Security and support for trust domain operation is described. An example of a method includes processing, at an accelerator, one or more compute workloads received from a host system; upon receiving a notification that a trust domain has transitioned to a secure state, transition an original set of privileges for the accelerator to a downgraded set of privileges; upon receiving a command from the host system for the trust domain, processing the command in accordance with the trust domain; and upon receiving a request from the host system to access a register, for a register included in an allowed list of registers for access, allow access to the register, and, for a register that is not within the allowed list of registers for access, disallowing access to the register.
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公开(公告)号：US09542336B2
公开(公告)日：2017-01-10
申请号：US14133097
申请日：2013-12-18
Applicant: INTEL CORPORATION
Inventor： Marc Torrant , David Puffer , Blaise Fanning , Bryan White , Joydeep Ray , Neil Schaper , Todd Witter , Altug Koker , Aditya Sreenivas
CPC classification number: G06F12/126
Abstract: A processing device comprises an instruction execution unit, a memory agent and pinning logic to pin memory pages in a multi-level memory system upon request by the memory agent. The pinning logic includes an agent interface module to receive, from the memory agent, a pin request indicating a first memory page in the multi-level memory system, the multi-level memory system comprising a near memory and a far memory. The pinning logic further includes a memory interface module to retrieve the first memory page from the far memory and write the first memory page to the near memory. In addition, the pinning logic also includes a descriptor table management module to mark the first memory page as pinned in the near memory, wherein marking the first memory page as pinned comprises setting a pinning bit corresponding to the first memory page in a cache descriptor table and to prevent the first memory page from being evicted from the near memory when the first memory page is marked as pinned.
Abstract translation: 处理设备包括指令执行单元，存储器代理和钉住逻辑，以在存储器请求时针对多级存储器系统中的存储器页面进行引脚。 钉扎逻辑包括代理接口模块，用于从存储器代理接收指示多级存储器系统中的第一存储器页的引脚请求，所述多级存储器系统包括近存储器和远存储器。 钉扎逻辑还包括存储器接口模块，用于从远端存储器检索第一存储器页面，并将第一存储器页面写入近端存储器。 此外，钉扎逻辑还包括描述符表管理模块，用于将第一存储器页标记为固定在近存储器中，其中将第一存储器页标记为固定包括将对应于第一存储器页的锁存位设置在高速缓存描述符表中 并且当第一存储器页面被标记为被固定时，防止第一存储器页被从近存储器逐出。
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