公开(公告)号：US20200244269A1

公开(公告)日：2020-07-30

申请号：US16780790

申请日：2020-02-03

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava

IPC: H03L1/00 ,  H03L7/099 ,  H03K3/03

Abstract: An apparatus is provided which comprises: a first ring oscillator comprising at least one aging tolerant circuitry; a second ring oscillator comprising a non-aging tolerant circuitry; a first counter coupled to the first ring oscillator, wherein the first counter is to count a frequency of the first ring oscillator; a second counter coupled to the second ring oscillator, wherein the second counter is to count a frequency of the second ring oscillator; and logic to compare the frequencies of the first and second ring oscillators, and to generate one or more controls to mitigate aging of one or more devices.

公开(公告)号：US20190251055A1

公开(公告)日：2019-08-15

申请号：US16396153

申请日：2019-04-26

Applicant: Intel Corporation

Inventor： Chih-Cheh Chen ,  Janusz P. Jurski ,  Amit Kumar Srivastava ,  Malay Trivedi ,  James Mitchell ,  Piotr Michael Kwidzinski ,  David N. Lombard

IPC: G06F13/40 ,  G06F13/42 ,  G06F1/329 ,  G06F1/3228 ,  G06F1/3234 ,  G06F9/38

CPC classification number: G06F13/4068 ,  G06F1/3228 ,  G06F1/3253 ,  G06F1/329 ,  G06F9/3877 ,  G06F13/4221 ,  G06F2212/1028

Abstract: An apparatus includes physical layer circuitry with lanes to couple the apparatus to endpoint devices. a first input/output (I/O) controller to couple a first processor to the physical layer circuitry, and a second I/O controller to couple a second processor to the physical layer circuitry. The first and second I/O controllers are compatible with a Peripheral Component Interconnect Express (PCIe)-based protocol. The apparatus also includes a flexible input/output adapter (FIA) coupling the first and second I/O controllers to the lanes. The FIA selectively assigns access to each lane of the lanes by either the first or second I/O controller. The apparatus also includes a power management controller (PMC) communicably coupled to the FIA. The PMC causes the FIA to dynamically assign access to at least one of the lanes by the first or second I/O controller without a reboot cycle.

公开(公告)号：US10320430B2

公开(公告)日：2019-06-11

申请号：US15721535

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava

IPC: G06F1/30 ,  H04B1/04 ,  G06F13/40 ,  H04B1/16

Abstract: Described is an apparatus which comprises: a driver comprising a push-pull transmitter; a first circuitry to sense variation in a power supply; and a second circuitry coupled to the first circuitry and to the driver, the second circuitry to generate a code according to an output of the first circuitry, wherein the code is provided to the driver to adjust a performance parameter of the driver.

公开(公告)号：US10241536B2

公开(公告)日：2019-03-26

申请号：US15366001

申请日：2016-12-01

Applicant: Intel Corporation

Inventor： Duane G. Quiet ,  Amit Kumar Srivastava ,  Kenneth P. Foust

IPC: G06F9/00 ,  G06F1/08 ,  G06F13/362

Abstract: In one embodiment, an apparatus includes a clock control circuit to generate a clock signal for communication on an interconnect. The clock control circuit may be configured to receive an indication of a next device of a plurality of devices to be accessed and to dynamically update a control signal to cause the communication of the clock signal to be dynamically switched between a fixed clock frequency and a spread spectrum clock frequency based at least in part on the indication of communication to the next device. Other embodiments are described and claimed.

公开(公告)号：US20190028139A1

公开(公告)日：2019-01-24

申请号：US15845355

申请日：2017-12-18

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava

IPC: H04B1/7097 ,  H04B1/7073 ,  H04L7/04 ,  H04L7/00

CPC classification number: H04B1/7097 ,  H04B1/7073 ,  H04B15/04 ,  H04B2201/7073 ,  H04L7/0025 ,  H04L7/0029 ,  H04L7/0087 ,  H04L7/0337 ,  H04L7/048

Abstract: An apparatus is provided which comprises: a first circuitry to track a spread spectrum of a differential signal according to sampled data; and a second circuitry to adjust phase of a clock according to the spread spectrum, wherein the clock is used for sampling the differential signal.

公开(公告)号：US10116313B2

公开(公告)日：2018-10-30

申请号：US14835656

申请日：2015-08-25

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava

IPC: H03L7/00 ,  H03L7/08 ,  H03L7/06 ,  H03L7/087 ,  H03L7/089 ,  H03L7/07 ,  H03L7/23 ,  H03L7/197 ,  H03M1/50

Abstract: Described is an apparatus which comprises: a first clocking source having a first divider; a second clocking source having a second divider, wherein the first and second clocking sources are inductively coupled; and calibration logic to monitor clock signals associated with the first and second clocking sources and to generate at least one calibration code for adjusting at least one divider ratio of the first or second dividers according to the monitored clock signals.

公开(公告)号：US10031882B2

公开(公告)日：2018-07-24

申请号：US15086700

申请日：2016-03-31

Applicant: INTEL CORPORATION

Inventor： Amit Kumar Srivastava

IPC: G06F13/42 ,  G06F13/364 ,  G06F13/16 ,  G06F1/32

Abstract: Described is an I3C Repeater. The I3C Repeater may have a first circuitry with an I3C interface, a second circuitry with an I2C interface, and a datapath circuitry coupled to the first circuitry and the second circuitry. The second circuitry may be operable to convert a transaction received on the I2C interface into a transaction for the I3C interface, and to convert a transaction received on the I3C interface into a transaction for the I2C interface. The I3C Repeater may also have additional circuitries operable to convert transactions received on one of an SPI interface, a UART interface, and a Debug bus interface into transactions for the I3C interface, and vice-versa.

公开(公告)号：US20180189222A1

公开(公告)日：2018-07-05

申请号：US15396376

申请日：2016-12-30

Applicant: INTEL CORPORATION

Inventor： Amit Kumar Srivastava

IPC: G06F13/42 ,  G06F13/28

CPC classification number: G06F13/4282 ,  G06F13/287 ,  G06F13/387 ,  G06F2213/0026 ,  G06F2213/4002

Abstract: Methods and apparatuses relating to circuitry for multilane serial bus communications are described. In an embodiment, an apparatus includes a serial bus controller, upstream serial bus lanes, a single downstream serial bus lane, and a host/device lane controller. The serial bus controller is to send and receive data transmissions to and from serial bus devices. The upstream serial bus lanes correspond to the serial bus devices and are associated with serial port addresses. The host/device lane controller is to receive data transmissions through the upstream serial bus lanes and includes a port address assignment circuit and a multiplexer. The port address assignment circuit is to assign serial port addresses to data transmissions, to be included in data transmissions to identify the upstream serial bus lanes through which the data transmission was received. The multiplexer is to forward data transmissions from upstream serial bus lanes to the downstream serial bus lane.

公开(公告)号：US20180181507A1

公开(公告)日：2018-06-28

申请号：US15474117

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Kenneth P. Foust ,  Duane G. Quiet ,  Amit Kumar Srivastava

IPC: G06F13/24 ,  G06F13/42

CPC classification number: G06F13/24 ,  G06F13/4282

Abstract: Embodiments of the present disclosure may relate to a host controller that includes processing circuitry to identify an inter-integrated circuit (I2C) out-of-band interrupt (OBI) received on a general purpose input-output (GPIO) pin from an I2C device that is unable to generate an improved inter-integrated circuit (I3C) bus an I3C in-band interrupt (IBI). The processing circuitry may further generate, based on the I2C OBI, an I3C IBI that includes information related to the I2C OBI. The host controller may further include transmission circuitry to transmit the I3C IBI on an I3C bus. Other embodiments may be described and/or claimed.

公开(公告)号：US20180052791A1

公开(公告)日：2018-02-22

申请号：US15237928

申请日：2016-08-16

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava ,  Duane G. Quiet ,  Kenneth P. Foust

IPC: G06F13/364 ,  G06F13/42 ,  G06F1/32

CPC classification number: G06F13/364 ,  G06F1/3253 ,  G06F1/3287 ,  G06F1/3296 ,  G06F13/4282 ,  Y02D10/151 ,  Y02D50/20

Abstract: In an embodiment, a host device includes: a transceiver to communicate information on an interconnect; a controller to control operation of the transceiver and to be a master for the interconnect; and a role transfer logic to cause a secondary device to be the master for the interconnect when at least a portion of the host device is to enter into a low power. Other embodiments are described and claimed.