公开(公告)号：US09594717B2

公开(公告)日：2017-03-14

申请号：US14671947

申请日：2015-03-27

Applicant: INTEL CORPORATION

Inventor： Kimberly Davis ,  Mark Sullivan ,  James Mitchell ,  Patrick Themins

IPC: G06F13/20 ,  G06F13/42 ,  G06F11/07 ,  G06F13/40 ,  G06F13/24 ,  G06F11/20

CPC classification number: G06F13/4221 ,  G06F11/0709 ,  G06F11/0757 ,  G06F11/2038 ,  G06F11/2043 ,  G06F13/24 ,  G06F13/4059

Abstract: A dual host system and method with back to back non-transparent bridges and a proxy packet generating mechanism. The proxy packet generating mechanism enables the hosts to send interrupt generating packets to each other.

Abstract translation: 具有背对背非透明网桥和代理数据包生成机制的双主机系统和方法。 代理分组生成机制使得主机能够相互发送中断生成分组。

公开(公告)号：US12229073B2

公开(公告)日：2025-02-18

申请号：US17340315

申请日：2021-06-07

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava ,  Divya Gupta ,  Michael Karas ,  James Mitchell ,  Malay Trivedi ,  Chung-Chi Wang

IPC: G06F13/42 ,  G06F13/40 ,  G06F15/78

Abstract: In one embodiment, an apparatus includes: a plurality of cores to execute instructions; a firmware agent to execute a first firmware; a Peripheral Component Interconnect Express (PCIe) interface to communicate with a device via a PCIe link; and a boot agent coupled to the PCIe interface to download the PCIe firmware from a non-volatile memory and provide the PCIe firmware to the PCIe interface. The PCIe interface may receive a PCIe firmware for the PCIe interface before the firmware agent is to receive the first firmware. Other embodiments are described and claimed.

公开(公告)号：US20210294772A1

公开(公告)日：2021-09-23

申请号：US17340315

申请日：2021-06-07

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava ,  Divya Gupta ,  Michael Karas ,  James Mitchell ,  Malay Trivedi ,  Chung-Chi Wang

IPC: G06F13/42 ,  G06F15/78 ,  G06F9/445 ,  G06F13/40 ,  G06F9/4401

Abstract: In one embodiment, an apparatus includes: a plurality of cores to execute instructions; a firmware agent to execute a first firmware; a Peripheral Component Interconnect Express (PCIe) interface to communicate with a device via a PCIe link; and a boot agent coupled to the PCIe interface to download the PCIe firmware from a non-volatile memory and provide the PCIe firmware to the PCIe interface. The PCIe interface may receive a PCIe firmware for the PCIe interface before the firmware agent is to receive the first firmware. Other embodiments are described and claimed.

公开(公告)号：US10817454B2

公开(公告)日：2020-10-27

申请号：US16396153

申请日：2019-04-26

Applicant: Intel Corporation

Inventor： Chih-Cheh Chen ,  Janusz P. Jurski ,  Amit Kumar Srivastava ,  Malay Trivedi ,  James Mitchell ,  Piotr Michael Kwidzinski ,  David N. Lombard

IPC: G06F13/40 ,  G06F13/42 ,  G06F1/329 ,  G06F1/3234 ,  G06F9/38 ,  G06F1/3228

Abstract: An apparatus includes physical layer circuitry with lanes to couple the apparatus to endpoint devices. a first input/output (I/O) controller to couple a first processor to the physical layer circuitry, and a second I/O controller to couple a second processor to the physical layer circuitry. The first and second I/O controllers are compatible with a Peripheral Component Interconnect Express (PCIe)-based protocol. The apparatus also includes a flexible input/output adapter (FIA) coupling the first and second I/O controllers to the lanes. The FIA selectively assigns access to each lane of the lanes by either the first or second I/O controller. The apparatus also includes a power management controller (PMC) communicably coupled to the FIA. The PMC causes the FIA to dynamically assign access to at least one of the lanes by the first or second I/O controller without a reboot cycle.

公开(公告)号：US20190251055A1

公开(公告)日：2019-08-15

申请号：US16396153

申请日：2019-04-26

Applicant: Intel Corporation

Inventor： Chih-Cheh Chen ,  Janusz P. Jurski ,  Amit Kumar Srivastava ,  Malay Trivedi ,  James Mitchell ,  Piotr Michael Kwidzinski ,  David N. Lombard

IPC: G06F13/40 ,  G06F13/42 ,  G06F1/329 ,  G06F1/3228 ,  G06F1/3234 ,  G06F9/38

CPC classification number: G06F13/4068 ,  G06F1/3228 ,  G06F1/3253 ,  G06F1/329 ,  G06F9/3877 ,  G06F13/4221 ,  G06F2212/1028

Abstract: An apparatus includes physical layer circuitry with lanes to couple the apparatus to endpoint devices. a first input/output (I/O) controller to couple a first processor to the physical layer circuitry, and a second I/O controller to couple a second processor to the physical layer circuitry. The first and second I/O controllers are compatible with a Peripheral Component Interconnect Express (PCIe)-based protocol. The apparatus also includes a flexible input/output adapter (FIA) coupling the first and second I/O controllers to the lanes. The FIA selectively assigns access to each lane of the lanes by either the first or second I/O controller. The apparatus also includes a power management controller (PMC) communicably coupled to the FIA. The PMC causes the FIA to dynamically assign access to at least one of the lanes by the first or second I/O controller without a reboot cycle.