公开(公告)号：US12125121B2

公开(公告)日：2024-10-22

申请号：US17211095

申请日：2021-03-24

Applicant: Intel Corporation

Inventor： Amandeep Singh ,  Arthur Hunter, Jr. ,  Abhinav Srivastava ,  Rashmi Agarwal ,  Mohit Choradia

IPC: G06T1/20 ,  G06T1/60 ,  G06T17/20

CPC classification number: G06T1/20 ,  G06T1/60 ,  G06T17/20 ,  G06T2210/52

Abstract: An apparatus to facilitate tessellation redistribution for reducing latencies in processors is disclosed. The apparatus includes a processor to provide parallel interconnected geometry fixed-function units with separate front end and back ends, the front ends to perform patch culling and transmission and the back ends to perform patch reception from the front end and patch tessellation; provide a tessellation redistribution central engine to redistribute patches among the back ends using a redistribution bus; receive, by the tessellation redistribution central engine from the front ends in parallel, patch transmissions marked for distribution, the tessellation redistribution engine to process the patch transmissions in order; and in response to receiving a synchronization barrier packet from one of the front ends, broadcast, by the tessellation redistribution central engine, the synchronization barrier packet to the back ends to cause one of the back ends to process tessellation work locally.

公开(公告)号：US20220197800A1

公开(公告)日：2022-06-23

申请号：US17428539

申请日：2020-03-14

Applicant: Intel Corporation

Inventor： Abhishek Appu ,  Lakshminarayanan Striramassarma ,  Altug Koker ,  Sean Coleman ,  Varghese George ,  Arthur Hunter, Jr. ,  Brent Insko ,  Scott Janus ,  Elmoustapha Ould-Ahmed-Vall ,  Vasanth Ranganathan ,  Joydeep Ray ,  Kamal Sinha ,  Prasoonkumar Surti ,  Karthik Vaidyanathan

IPC: G06F12/0811 ,  G06F12/0804 ,  G06F12/0893 ,  G06F12/0866 ,  G06F12/0891 ,  G06F12/0882 ,  G06F12/02 ,  G06F12/06

Abstract: Graphics processors of the present design provide hierarchical open sectors and variable cache sizes for cache operations. In one embodiment, a graphics processor comprises a cache memory having a hierarchical open sector design including a first hierarchy of upper and lower regions with each region including a second hierarchy of sectors. A cache controller is configured to initially open a first sector of the lower region, to receive a memory request that does not match an address in the first sector, and to open a second sector of the lower region.

公开(公告)号：US20220179787A1

公开(公告)日：2022-06-09

申请号：US17428530

申请日：2020-03-14

Applicant: Intel Corporation

Inventor： Altug Koker ,  Joydeep Ray ,  Ben Ashbaugh ,  Jonathan Pearce ,  Abhishek Appu ,  Vasanth Ranganathan ,  Lakshminarayanan Striramassarma ,  Elmoustapha Ould-Ahmed-Vall ,  Aravindh Anantaraman ,  Valentin Andrei ,  Nicolas Galoppo Von Borries ,  Varghese George ,  Yoav Harel ,  Arthur Hunter, Jr. ,  Brent Insko ,  Scott Janus ,  Pattabhiraman K ,  Mike Macpherson ,  Subramaniam Maiyuran ,  Marian Alin Petre ,  Murali Ramadoss ,  Shailesh Shah ,  Kamal Sinha ,  Prasoonkumar Surti ,  Vikranth Vemulapalli

IPC: G06F12/0802 ,  G06F9/30

Abstract: Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache coupled to the processing resources. The cache controller is configured to control cache priority by determining whether default settings or an instruction will control cache operations for the cache.

公开(公告)号：US11113784B2

公开(公告)日：2021-09-07

申请号：US17064427

申请日：2020-10-06

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Scott Janus ,  Varghese George ,  Subramaniam Maiyuran ,  Altug Koker ,  Abhishek Appu ,  Prasoonkumar Surti ,  Vasanth Ranganathan ,  Andrei Valentin ,  Ashutosh Garg ,  Yoav Harel ,  Arthur Hunter, Jr. ,  SungYe Kim ,  Mike Macpherson ,  Elmoustapha Ould-Ahmed-Vall ,  William Sadler ,  Lakshminarayanan Striramassarma ,  Vikranth Vemulapalli

IPC: G06T1/20 ,  G06F9/50 ,  G06F15/80 ,  G06F12/0806 ,  G06F17/16 ,  G06N3/04 ,  G06N3/08 ,  G06F7/544

Abstract: Embodiments described herein include, software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. Embodiment described herein provided techniques to skip computational operations for zero filled matrices and sub-matrices. Embodiments additionally provide techniques to maintain data compression through to a processing unit. Embodiments additionally provide an architecture for a sparse aware logic unit.