公开(公告)号：US11709793B2

公开(公告)日：2023-07-25

申请号：US17827067

申请日：2022-05-27

Applicant: Intel Corporation

Inventor： Subramaniam Maiyuran ,  Shubra Marwaha ,  Ashutosh Garg ,  Supratim Pal ,  Jorge Parra ,  Chandra Gurram ,  Varghese George ,  Darin Starkey ,  Guei-Yuan Lueh

IPC: G06T15/06 ,  G06F9/30 ,  G06F15/78 ,  G06F9/38 ,  G06F17/18 ,  G06F12/0802 ,  G06F7/544 ,  G06F7/575 ,  G06F12/02 ,  G06F12/0866 ,  G06F12/0875 ,  G06F12/0895 ,  G06F12/128 ,  G06F12/06 ,  G06F12/1009 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06F12/0811 ,  G06F15/80 ,  G06F17/16 ,  G06F7/58 ,  G06F12/0871 ,  G06F12/0862 ,  G06F12/0897 ,  G06F9/50 ,  G06F12/0804 ,  G06F12/0882 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0888 ,  G06N3/08

CPC classification number: G06F15/7839 ,  G06F7/5443 ,  G06F7/575 ,  G06F7/588 ,  G06F9/3001 ,  G06F9/3004 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30065 ,  G06F9/30079 ,  G06F9/3887 ,  G06F9/5011 ,  G06F9/5077 ,  G06F12/0215 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/0607 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/8046 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/3867 ,  G06F2212/1008 ,  G06F2212/1021 ,  G06F2212/1044 ,  G06F2212/302 ,  G06F2212/401 ,  G06F2212/455 ,  G06F2212/60 ,  G06N3/08 ,  G06T15/06

Abstract: Described herein is a graphics processing unit (GPU) comprising a first processing cluster to perform parallel processing operations, the parallel processing operations including a ray tracing operation and a matrix multiply operation; and a second processing cluster coupled to the first processing cluster, wherein the first processing cluster includes a floating-point unit to perform floating point operations, the floating-point unit is configured to process an instruction using a bfloat16 (BF16) format with a multiplier to multiply second and third source operands while an accumulator adds a first source operand with output from the multiplier.

公开(公告)号：US11361496B2

公开(公告)日：2022-06-14

申请号：US17304092

申请日：2021-06-14

Applicant: Intel Corporation

Inventor： Subramaniam Maiyuran ,  Shubra Marwaha ,  Ashutosh Garg ,  Supratim Pal ,  Jorge Parra ,  Chandra Gurram ,  Varghese George ,  Darin Starkey ,  Guei-Yuan Lueh

IPC: G06T15/06 ,  G06F9/30 ,  G06F9/38 ,  G06F17/18

Abstract: Described herein is a graphics processing unit (GPU) comprising a single instruction, multiple thread (SIMT) multiprocessor comprising an instruction cache, a shared memory coupled with the instruction cache, and circuitry coupled with the shared memory and the instruction cache, the circuitry including multiple texture units, a first core including hardware to accelerate matrix operations, and a second core configured to receive an instruction having multiple operands in a bfloat16 (BF16) number format, wherein the multiple operands include a first source operand, a second source operand, and a third source operand, and the BF16 number format is a sixteen-bit floating point format having an eight-bit exponent and process the instruction, wherein to process the instruction includes to multiply the second source operand by the third source operand and add a first source operand to a result of the multiply.

公开(公告)号：US11188618B2

公开(公告)日：2021-11-30

申请号：US16561715

申请日：2019-09-05

Applicant: Intel Corporation

Inventor： Subramaniam Maiyuran ,  Mathew Nevin ,  Jorge Parra ,  Ashutosh Garg ,  Shubra Marwaha ,  Shubh Shah

IPC: G06F17/16 ,  G06F7/487 ,  G06F9/30 ,  G06F13/16

Abstract: An apparatus to facilitate acceleration of matrix multiplication operations. The apparatus comprises a systolic array including matrix multiplication hardware to perform multiply-add operations on received matrix data comprising data from a plurality of input matrices and sparse matrix acceleration hardware to detect zero values in the matrix data and perform one or more optimizations on the matrix data to reduce multiply-add operations to be performed by the matrix multiplication hardware.

公开(公告)号：US11113784B2

公开(公告)日：2021-09-07

申请号：US17064427

申请日：2020-10-06

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Scott Janus ,  Varghese George ,  Subramaniam Maiyuran ,  Altug Koker ,  Abhishek Appu ,  Prasoonkumar Surti ,  Vasanth Ranganathan ,  Andrei Valentin ,  Ashutosh Garg ,  Yoav Harel ,  Arthur Hunter, Jr. ,  SungYe Kim ,  Mike Macpherson ,  Elmoustapha Ould-Ahmed-Vall ,  William Sadler ,  Lakshminarayanan Striramassarma ,  Vikranth Vemulapalli

IPC: G06T1/20 ,  G06F9/50 ,  G06F15/80 ,  G06F12/0806 ,  G06F17/16 ,  G06N3/04 ,  G06N3/08 ,  G06F7/544

Abstract: Embodiments described herein include, software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. Embodiment described herein provided techniques to skip computational operations for zero filled matrices and sub-matrices. Embodiments additionally provide techniques to maintain data compression through to a processing unit. Embodiments additionally provide an architecture for a sparse aware logic unit.

公开(公告)号：US10360654B1

公开(公告)日：2019-07-23

申请号：US15990328

申请日：2018-05-25

Applicant: Intel Corporation

Inventor： Subramaniam Maiyuran ,  Supratim Pal ,  Jorge E. Parra ,  Chandra S. Gurram ,  Ashwin J. Shivani ,  Ashutosh Garg ,  Brent A. Schwartz ,  Jorge F. Garcia Pabon ,  Darin M. Starkey ,  Shubh B. Shah ,  Guei-Yuan Lueh ,  Kaiyu Chen ,  Konrad Trifunovic ,  Buqi Cheng ,  Weiyu Chen

IPC: G06F9/38 ,  G06F8/41 ,  G06T1/20 ,  G06F9/30 ,  G06T1/60 ,  G09G5/36 ,  G06T15/00

Abstract: Embodiments described herein provide a graphics processor in which dependency tracking hardware is simplified via the use of compiler provided software scoreboard information. In one embodiment the shader compiler for shader programs is configured to encode software scoreboard information into each instruction. Dependencies can be evaluated by the shader compiler and provided as scoreboard information with each instruction. The hardware can then use the provided information when scheduling instructions. In one embodiment, a software scoreboard synchronization instruction is provided to facilitate software dependency handling within a shader program. Using software to facilitate software dependency handling and synchronization can simplify hardware design, reducing the area consumed by the hardware. In one embodiment, dependencies can be evaluated by the shader compiler instead of the GPU hardware. The compiler can then insert a software scoreboard sync immediate instruction into compiled program code to manage instruction dependencies and prevent data hazards from occurring.

公开(公告)号：US20250166114A1

公开(公告)日：2025-05-22

申请号：US18967123

申请日：2024-12-03

Applicant: Intel Corporation

Inventor： Abhishek Appu ,  Subramaniam Maiyuran ,  Mike Macpherson ,  Fangwen Fu ,  Jiasheng Chen ,  Varghese George ,  Vasanth Ranganathan ,  Ashutosh Garg ,  Joydeep Ray

IPC: G06T1/20 ,  G06F7/544 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F12/0806 ,  G06F15/80 ,  G06F17/16 ,  G06N3/048 ,  G06N3/08 ,  G06N3/084

Abstract: Embodiments described herein include software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. One embodiment provides for data aware sparsity via compressed bitstreams. One embodiment provides for block sparse dot product instructions. One embodiment provides for a depth-wise adapter for a systolic array.

公开(公告)号：US12007935B2

公开(公告)日：2024-06-11

申请号：US17428523

申请日：2020-03-14

Applicant: INTEL CORPORATION

Inventor： Subramaniam Maiyuran ,  Shubra Marwaha ,  Ashutosh Garg ,  Supratim Pal ,  Jorge Parra ,  Chandra Gurram ,  Varghese George ,  Darin Starkey ,  Guei-Yuan Lueh

IPC: G06F9/30 ,  G06F7/544 ,  G06F7/575 ,  G06F7/58 ,  G06F9/38 ,  G06F9/50 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/78 ,  G06F15/80 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06N3/08 ,  G06T15/06

CPC classification number: G06F15/7839 ,  G06F7/5443 ,  G06F7/575 ,  G06F7/588 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30065 ,  G06F9/30079 ,  G06F9/3887 ,  G06F9/5011 ,  G06F9/5077 ,  G06F12/0215 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/0607 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/8046 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/3867 ,  G06F2212/1008 ,  G06F2212/1021 ,  G06F2212/1044 ,  G06F2212/302 ,  G06F2212/401 ,  G06F2212/455 ,  G06F2212/60 ,  G06N3/08 ,  G06T15/06

Abstract: Graphics processors and graphics processing units having dot product accumulate instructions for a hybrid floating point format are disclosed. In one embodiment, a graphics multiprocessor comprises an instruction unit to dispatch instructions and
a processing resource coupled to the instruction unit. The processing resource is configured to receive a dot product accumulate instruction from the instruction unit and to process the dot product accumulate instruction using a bfloat16 number (BF16) format.

公开(公告)号：US11954063B2

公开(公告)日：2024-04-09

申请号：US18170900

申请日：2023-02-17

Applicant: Intel Corporation

Inventor： Subramaniam Maiyuran ,  Shubra Marwaha ,  Ashutosh Garg ,  Supratim Pal ,  Jorge Parra ,  Chandra Gurram ,  Varghese George ,  Darin Starkey ,  Guei-Yuan Lueh

IPC: G06T15/06 ,  G06F7/544 ,  G06F7/575 ,  G06F7/58 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/78 ,  G06F15/80 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06N3/08

CPC classification number: G06F15/7839 ,  G06F7/5443 ,  G06F7/575 ,  G06F7/588 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30065 ,  G06F9/30079 ,  G06F9/3887 ,  G06F9/5011 ,  G06F9/5077 ,  G06F12/0215 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/0607 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/8046 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/3867 ,  G06F2212/1008 ,  G06F2212/1021 ,  G06F2212/1044 ,  G06F2212/302 ,  G06F2212/401 ,  G06F2212/455 ,  G06F2212/60 ,  G06N3/08 ,  G06T15/06

Abstract: Described herein is a graphics processing unit (GPU) configured to receive an instruction having multiple operands, where the instruction is a single instruction multiple data (SIMD) instruction configured to use a bfloat16 (BF16) number format and the BF16 number format is a sixteen-bit floating point format having an eight-bit exponent. The GPU can process the instruction using the multiple operands, where to process the instruction includes to perform a multiply operation, perform an addition to a result of the multiply operation, and apply a rectified linear unit function to a result of the addition.

公开(公告)号：US11669329B2

公开(公告)日：2023-06-06

申请号：US17723312

申请日：2022-04-18

Applicant: Intel Corporation

Inventor： Supratim Pal ,  Sasikanth Avancha ,  Ishwar Bhati ,  Wei-Yu Chen ,  Dipankar Das ,  Ashutosh Garg ,  Chandra S. Gurram ,  Junjie Gu ,  Guei-Yuan Lueh ,  Subramaniam Maiyuran ,  Jorge E. Parra ,  Sudarshan Srinivasan ,  Varghese George

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3802 ,  G06F9/3001 ,  G06F9/30018 ,  G06F9/30145

Abstract: Embodiments described herein provide for an instruction and associated logic to enable a vector multiply add instructions with automatic zero skipping for sparse input. One embodiment provides for a general-purpose graphics processor comprising logic to perform operations comprising fetching a hardware macro instruction having a predicate mask, a repeat count, and a set of initial operands, where the initial operands include a destination operand and multiple source operands. The hardware macro instruction is configured to perform one or more multiply/add operations on input data associated with a set of matrices.

公开(公告)号：US11416580B2

公开(公告)日：2022-08-16

申请号：US16682225

申请日：2019-11-13

Applicant: Intel Corporation

Inventor： Nevin Mathew ,  Shubra Marwaha ,  Ashutosh Garg

IPC: G06F17/16 ,  G06F9/30 ,  G06N3/08 ,  G06N20/10

Abstract: An apparatus to facilitate matrix multiplication operations. The apparatus comprises multiplication hardware to operate in a dot product mode, wherein a multiplication stage included in the multiplication hardware is configured as a dot product of a number of bit vectors (N) to perform N×N multiplication operations on a plurality of multiplicands and perform addition operations on results of the N×N multiplication operations.