公开(公告)号：US10331452B2

公开(公告)日：2019-06-25

申请号：US14126313

申请日：2013-06-27

Applicant: Intel Corporation

Inventor： Thilo Schmitt ,  Peter Lachner ,  Beeman Strong ,  Ofer Levy ,  Thomas Toll ,  Matthew Merten ,  Tong Li ,  Ravi Rajwar ,  Konrad Lai

IPC: G06F9/30 ,  G06F11/36

Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for tracking the mode of processing devices in an instruction tracing system. The method may include receiving an indication of a change in a current execution mode of the processing device. The method may also include determining that the current execution mode of the received indication is different than a value of an execution mode of a first execution mode (EM) packet previously-generated by the IT module. The method may also include generating, based on the determining that the current execution mode is different, a second EM packet that provides a value of the current execution mode of the processing device to indicate the change in the execution mode for an instruction in a trace generated by the IT module. The method may further include generating transactional memory (TMX) packets having n bit mode pattern in the packet log. The n is at least two and the n bit mode indicates transaction status of the TMX operation.

公开(公告)号：US12189509B2

公开(公告)日：2025-01-07

申请号：US18252659

申请日：2020-12-24

Applicant: Intel Corporation

Inventor： Wei Wang ,  Matthew Merten ,  Beeman Strong ,  Andreas Kleen ,  Kan Liang ,  Gilbert Neiger ,  Kun Tian ,  Like Xu

IPC: G06F11/00 ,  G06F9/455 ,  G06F11/07 ,  G06F11/34

Abstract: In an embodiment, a processor for redirecting requests includes a processing engine to execute a guest system, and monitoring circuitry coupled to the processing engine. The monitoring circuitry may be to: receive, from the guest system, a first request to access a first virtual counter; in response to a receipt of the first request, determine, based a mapping register of the processor, a first physical counter mapped to the first virtual counter; and redirect the first request to the first physical counter mapped to the first virtual counter. Other embodiments are described and claimed.

公开(公告)号：US11900115B2

公开(公告)日：2024-02-13

申请号：US18126920

申请日：2023-03-27

Applicant: Intel Corporation

Inventor： Ashok Raj ,  Andreas Kleen ,  Gilbert Neiger ,  Beeman Strong ,  Jason Brandt ,  Rupin Vakharwala ,  Jeff Huxel ,  Larisa Novakovsky ,  Ido Ouziel ,  Sarathy Jayakumar

IPC: G06F9/30 ,  G06F15/80 ,  G06F9/50 ,  G06F9/48

CPC classification number: G06F9/30098 ,  G06F9/4812 ,  G06F9/5005 ,  G06F15/80

Abstract: An apparatus and method for processing non-maskable interrupt source information. For example, one embodiment of a processor comprises: a plurality of cores comprising execution circuitry to execute instructions and process data; local interrupt circuitry comprising a plurality of registers to store interrupt-related data including non-maskable interrupt (NMI) data related to a first NMI; and non-maskable interrupt (NMI) processing mode selection circuitry, responsive to a request, to select between at least two NMI processing modes to process the first NMI including: a first NMI processing mode in which the plurality of registers are to store first data related to a first NMI, wherein no NMI source information related to a source of the NMI is included in the first data, and a second NMI processing mode in which the plurality of registers are to store both the first data related to the first NMI and second data comprising NMI source information indicating the NMI source.

公开(公告)号：US20240012735A1

公开(公告)日：2024-01-11

申请号：US18252659

申请日：2020-12-24

Applicant: Intel Corporation

Inventor： Wei Wang ,  Matthew Merten ,  Beeman Strong ,  Andreas Kleen ,  Kan Liang ,  Gilbert Neiger ,  Kun Tian ,  Like Xu

IPC: G06F11/34 ,  G06F11/07 ,  G06F9/455

CPC classification number: G06F11/3466 ,  G06F11/0772 ,  G06F9/45545

Abstract: In an embodiment, a processor for redirecting requests includes a processing engine to execute a guest system, and monitoring circuitry coupled to the processing engine. The monitoring circuitry may be to: receive, from the guest system, a first request to access a first virtual counter; in response to a receipt of the first request, determine, based a mapping register of the processor, a first physical counter mapped to the first virtual counter; and redirect the first request to the first physical counter mapped to the first virtual counter. Other embodiments are described and claimed.

公开(公告)号：US11048512B1

公开(公告)日：2021-06-29

申请号：US16833598

申请日：2020-03-28

Applicant: Intel Corporation

Inventor： Ashok Raj ,  Andreas Kleen ,  Gilbert Neiger ,  Beeman Strong ,  Jason Brandt ,  Rupin Vakharwala ,  Jeff Huxel ,  Larisa Novakovsky ,  Ido Ouziel ,  Sarathy Jayakumar

IPC: G06F9/50 ,  G06F9/30 ,  G06F15/80 ,  G06F9/48

Abstract: An apparatus and method for processing non-maskable interrupt source information. For example, one embodiment of a processor comprises: a plurality of cores comprising execution circuitry to execute instructions and process data; local interrupt circuitry comprising a plurality of registers to store interrupt-related data including non-maskable interrupt (NMI) data related to a first NMI; and non-maskable interrupt (NMI) processing mode selection circuitry, responsive to a request, to select between at least two NMI processing modes to process the first NMI including: a first NMI processing mode in which the plurality of registers are to store first data related to a first NMI, wherein no NMI source information related to a source of the NMI is included in the first data, and a second NMI processing mode in which the plurality of registers are to store both the first data related to the first NMI and second data comprising NMI source information indicating the NMI source.