公开(公告)号：US20160188479A1

公开(公告)日：2016-06-30

申请号：US14977659

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Ravi Rajwar ,  Bret L. Toll ,  Konrad K. Lai ,  Matthew Merten ,  Martin G. Dixon

IPC: G06F12/08 ,  G06F9/30

CPC classification number: G06F11/28 ,  G06F9/30047 ,  G06F9/30076 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30098 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/3802 ,  G06F9/3834 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/466 ,  G06F9/467 ,  G06F11/1407 ,  G06F11/2236 ,  G06F11/25 ,  G06F11/263 ,  G06F12/0811 ,  G06F12/0828 ,  G06F12/084 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F2212/1032 ,  G06F2212/20 ,  G06F2212/283 ,  G06F2212/314 ,  G06F2212/452 ,  G06F2212/602 ,  G06F2212/608 ,  G06F2212/621 ,  G11C7/1072

Abstract: Novel instructions, logic, methods and apparatus are disclosed to test transactional execution status. Embodiments include decoding a first instruction to start a transactional region. Responsive to the first instruction, a checkpoint for a set of architecture state registers is generated and memory accesses from a processing element in the transactional region associated with the first instruction are tracked. A second instruction to detect transactional execution of the transactional region is then decoded. An operation is executed, responsive to decoding the second instruction, to determine if an execution context of the second instruction is within the transactional region. Then responsive to the second instruction, a first flag is updated. In some embodiments, a register may optionally be updated and/or a second flag may optionally be updated responsive to the second instruction.

公开(公告)号：US20230315470A1

公开(公告)日：2023-10-05

申请号：US17708933

申请日：2022-03-30

Applicant: Intel Corporation

Inventor： Matthew Merten ,  Beeman Strong ,  Moshe Cohen ,  Ahmad Yasin ,  Andreas Kleen ,  Stanislav Bratanov ,  Karthik Gopalakrishnan ,  Angela Schmid ,  Grant Zhou

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/32 ,  G06F11/34

CPC classification number: G06F9/3814 ,  G06F9/30101 ,  G06F9/321 ,  G06F11/3409

Abstract: Techniques and mechanisms for configuring processor event-based sampling (PEBS) with a set of control registers. In an embodiment, a first control register of a processor is programmed to store a physical address of a location in a buffer which receives PEBS records. The first control register is further programmed or otherwise configured to store an indication of a size of the buffer. A second control register of the processor stores a physical address of a location in the buffer were a next PEBS record is to be stored. In another embodiment, the processor further comprises multiple control registers which variously configure PEBS generation on a per-counter basis.

公开(公告)号：US20170161106A1

公开(公告)日：2017-06-08

申请号：US15385823

申请日：2016-12-20

Applicant: Intel Corporation

Inventor： Morris Marden ,  Matthew Merten ,  Alexandre Farcy ,  Avinash Sodani ,  James Hadley ,  Ilhyun Kim

IPC: G06F9/50 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F9/50 ,  G06F9/30101 ,  G06F9/3851 ,  G06F2209/5014

Abstract: A method and apparatus for providing fairness in a multi-processing element environment is herein described. Mask elements are utilized to associated portions of a reservation station with each processing element, while still allowing common access to another portion of reservation station entries. Additionally, bias logic biases selection of processing elements in a pipeline away from a processing element associated with a blocking stall to provide fair utilization of the pipeline.

公开(公告)号：US12189509B2

公开(公告)日：2025-01-07

申请号：US18252659

申请日：2020-12-24

Applicant: Intel Corporation

Inventor： Wei Wang ,  Matthew Merten ,  Beeman Strong ,  Andreas Kleen ,  Kan Liang ,  Gilbert Neiger ,  Kun Tian ,  Like Xu

IPC: G06F11/00 ,  G06F9/455 ,  G06F11/07 ,  G06F11/34

Abstract: In an embodiment, a processor for redirecting requests includes a processing engine to execute a guest system, and monitoring circuitry coupled to the processing engine. The monitoring circuitry may be to: receive, from the guest system, a first request to access a first virtual counter; in response to a receipt of the first request, determine, based a mapping register of the processor, a first physical counter mapped to the first virtual counter; and redirect the first request to the first physical counter mapped to the first virtual counter. Other embodiments are described and claimed.

公开(公告)号：US20240012735A1

公开(公告)日：2024-01-11

申请号：US18252659

申请日：2020-12-24

Applicant: Intel Corporation

Inventor： Wei Wang ,  Matthew Merten ,  Beeman Strong ,  Andreas Kleen ,  Kan Liang ,  Gilbert Neiger ,  Kun Tian ,  Like Xu

IPC: G06F11/34 ,  G06F11/07 ,  G06F9/455

CPC classification number: G06F11/3466 ,  G06F11/0772 ,  G06F9/45545

Abstract: In an embodiment, a processor for redirecting requests includes a processing engine to execute a guest system, and monitoring circuitry coupled to the processing engine. The monitoring circuitry may be to: receive, from the guest system, a first request to access a first virtual counter; in response to a receipt of the first request, determine, based a mapping register of the processor, a first physical counter mapped to the first virtual counter; and redirect the first request to the first physical counter mapped to the first virtual counter. Other embodiments are described and claimed.

公开(公告)号：US10956160B2

公开(公告)日：2021-03-23

申请号：US16367171

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Mark Dechene ,  Srikanth Srinivasan ,  Matthew Merten ,  Ammon Christiansen

IPC: G06F9/30 ,  G06F9/22 ,  G06F9/38 ,  G06F9/48

Abstract: A processor and method are described for a multi-level reservation station. For example, one embodiment of an apparatus comprises: execution circuitry comprising a plurality of functional units to execute a plurality of operations; a reservation station comprising a plurality of entries to store a corresponding plurality of operations to be executed on one or more of the functional units, the reservation station comprising: a first RS level to hold a first subset of the plurality of operations which are ready for execution by one or more functional units or which are expected to be ready for execution by the functional units; a second RS level to hold a second subset of the plurality of operations which are not expected to be ready for execution by the functional units; operation evaluation circuitry to evaluate operations in the first RS level and, responsive to identifying one or more operations which are not expected to be ready for execution, to cause the one or more operations to be moved from the first RS level to the second RS level.

公开(公告)号：US20200310801A1

公开(公告)日：2020-10-01

申请号：US16367171

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Mark Dechene ,  Srikanth Srinivasan ,  Matthew Merten ,  Ammon Christiansen

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F9/22

Abstract: A processor and method are described for a multi-level reservation station. For example, one embodiment of an apparatus comprises: execution circuitry comprising a plurality of functional units to execute a plurality of operations; a reservation station comprising a plurality of entries to store a corresponding plurality of operations to be executed on one or more of the functional units, the reservation station comprising: a first RS level to hold a first subset of the plurality of operations which are ready for execution by one or more functional units or which are expected to be ready for execution by the functional units; a second RS level to hold a second subset of the plurality of operations which are not expected to be ready for execution by the functional units; operation evaluation circuitry to evaluate operations in the first RS level and, responsive to identifying one or more operations which are not expected to be ready for execution, to cause the one or more operations to be moved from the first RS level to the second RS level.

公开(公告)号：US10409612B2

公开(公告)日：2019-09-10

申请号：US14998249

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Martin G. Dixon ,  Ravi Rajwar ,  Konrad K. Lai ,  Robert S. Chappell ,  Rajesh S. Parthasarathy ,  Alexandre J. Farcy ,  Ilhyun Kim ,  Prakash Math ,  Matthew Merten ,  Vijaykumar Kadgi

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/0875 ,  G06F12/0897 ,  G06F13/16 ,  G06F13/40 ,  G06F12/084 ,  G06F12/0895 ,  G06F13/42 ,  G06F12/0831 ,  G06F9/52 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/1027 ,  G06F9/46 ,  G06F12/0815 ,  G06F12/1045 ,  G06F12/0806

Abstract: An apparatus and method is described herein for providing robust speculative code section abort control mechanisms. Hardware is able to track speculative code region abort events, conditions, and/or scenarios, such as an explicit abort instruction, a data conflict, a speculative timer expiration, a disallowed instruction attribute or type, etc. And hardware, firmware, software, or a combination thereof makes an abort determination based on the tracked abort events. As an example, hardware may make an initial abort determination based on one or more predefined events or choose to pass the event information up to a firmware or software handler to make such an abort determination. Upon determining an abort of a speculative code region is to be performed, hardware, firmware, software, or a combination thereof performs the abort, which may include following a fallback path specified by hardware or software. And to enable testing of such a fallback path, in one implementation, hardware provides software a mechanism to always abort speculative code regions.

公开(公告)号：US10409611B2

公开(公告)日：2019-09-10

申请号：US14998248

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Martin G. Dixon ,  Ravi Rajwar ,  Konrad K. Lai ,  Robert S. Chappell ,  Rajesh S. Parthasarathy ,  Alexandre J. Farcy ,  Ilhyun Kim ,  Prakash Math ,  Matthew Merten ,  Vijaykumar Kadgi

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/0875 ,  G06F12/0897 ,  G06F13/16 ,  G06F13/40 ,  G06F12/084 ,  G06F12/0895 ,  G06F13/42 ,  G06F12/0831 ,  G06F9/52 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/1027 ,  G06F9/46 ,  G06F12/0815 ,  G06F12/1045 ,  G06F12/0806

Abstract: An apparatus and method is described herein for providing robust speculative code section abort control mechanisms. Hardware is able to track speculative code region abort events, conditions, and/or scenarios, such as an explicit abort instruction, a data conflict, a speculative timer expiration, a disallowed instruction attribute or type, etc. And hardware, firmware, software, or a combination thereof makes an abort determination based on the tracked abort events. As an example, hardware may make an initial abort determination based on one or more predefined events or choose to pass the event information up to a firmware or software handler to make such an abort determination. Upon determining an abort of a speculative code region is to be performed, hardware, firmware, software, or a combination thereof performs the abort, which may include following a fallback path specified by hardware or software. And to enable testing of such a fallback path, in one implementation, hardware provides software a mechanism to always abort speculative code regions.

公开(公告)号：US10331452B2

公开(公告)日：2019-06-25

申请号：US14126313

申请日：2013-06-27

Applicant: Intel Corporation

Inventor： Thilo Schmitt ,  Peter Lachner ,  Beeman Strong ,  Ofer Levy ,  Thomas Toll ,  Matthew Merten ,  Tong Li ,  Ravi Rajwar ,  Konrad Lai

IPC: G06F9/30 ,  G06F11/36

Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for tracking the mode of processing devices in an instruction tracing system. The method may include receiving an indication of a change in a current execution mode of the processing device. The method may also include determining that the current execution mode of the received indication is different than a value of an execution mode of a first execution mode (EM) packet previously-generated by the IT module. The method may also include generating, based on the determining that the current execution mode is different, a second EM packet that provides a value of the current execution mode of the processing device to indicate the change in the execution mode for an instruction in a trace generated by the IT module. The method may further include generating transactional memory (TMX) packets having n bit mode pattern in the packet log. The n is at least two and the n bit mode indicates transaction status of the TMX operation.