公开(公告)号：US20220414010A1

公开(公告)日：2022-12-29

申请号：US17704340

申请日：2022-03-25

Applicant: Intel Corporation

Inventor： Xiaodong Qiu ,  Yong Jiang ,  Changwon Rhee ,  Cui Tang ,  Shuangpeng Zhou ,  Lei Chen ,  Danyu Bi ,  Peiqing Jiang ,  Chengxi Wu

IPC: G06F12/084 ,  G06F9/48

Abstract: Embodiments are generally directed to methods and apparatuses for dynamically changing data priority in a cache. An embodiment of an apparatus comprising: a priority controller to: receive a memory access request to request data; and set a priority flag for the memory access request based on an accumulated access amount of data stored in a memory block to be accessed by the memory access request to dynamically change a priority level of the requested data.

公开(公告)号：US20220413854A1

公开(公告)日：2022-12-29

申请号：US17358859

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Supratim Pal ,  Prathamesh Raghunath Shinde ,  Ben J. Ashbaugh ,  Changwon Rhee ,  Hong Jiang ,  FangWen Fu

IPC: G06F9/30 ,  G06F9/38 ,  G06T15/00

Abstract: An apparatus to facilitate 64-bit two-dimensional (2D) block load with transpose is disclosed. The apparatus includes a processor comprising processing resources; and load store pipeline hardware circuitry coupled to the processing resources, the load store pipeline hardware circuitry to receive a 64-bit two-dimensional (2D) block load message with transpose from the processing resources. The load store pipeline hardware circuitry comprising a load store pipeline sequencer to map rows of a block of memory corresponding to the 64-bit 2D block load message with transpose to 64-bit standard load messages; and load store pipeline return circuitry to: sequentially number general register files (GRFs) used for returning elements of the block of memory accessed by the 64-bit standard load messages to the processing resources; and return, to the processing resources, the sequentially numbered GRFs in response to the 64-bit 2D block load message with transpose.

公开(公告)号：US20220413848A1

公开(公告)日：2022-12-29

申请号：US17358867

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Supratim Pal ,  Li-An Tang ,  Changwon Rhee ,  Timothy R. Bauer ,  Alexander Lyashevsky ,  Jiasheng Chen

IPC: G06F9/30 ,  G06F7/44 ,  G06F7/506 ,  G06F7/57 ,  G06F9/38

Abstract: An apparatus to facilitate large integer multiplication enhancements in a graphics environment is disclosed. The apparatus includes a processor comprising processing resources, the processing resources comprising multiplier circuitry to: receive operands for a multiplication operation, wherein the multiplication operation is part of a chain of multiplication operations for a large integer multiplication; and issue a multiply and add (MAD) instruction for the multiplication operation utilizing at least one of a double precision multiplier or a 48 bit output, wherein the MAD instruction to generate an output in a single clock cycle of the processor.

公开(公告)号：US10484640B2

公开(公告)日：2019-11-19

申请号：US15570640

申请日：2015-06-03

Applicant: INTEL CORPORATION

Inventor： Yunbiao Lin ,  Changliang Wang ,  Tiehan Lu ,  Qingyuan Zhang ,  Li Xu ,  Bo Zhao ,  Changwon Rhee

IPC: H04N5/445 ,  G06T1/60

Abstract: Techniques related to compositing video content are discussed. Such techniques may include generating transparency data for a surface of first video content and storing it in a stream out buffer, accessing the transparency data via the stream out buffer when there is no change to the surface of the first video content, and compositing the first video content with second video content based on the accessed transparency data.