公开(公告)号：US20240273851A1

公开(公告)日：2024-08-15

申请号：US18569570

申请日：2021-11-25

Applicant: Intel Corporation

Inventor： Changliang Wang ,  Juan Zhao ,  Gang Shen ,  Wei Zong

IPC: G06V10/10 ,  G06T5/50 ,  G06T7/11 ,  G06T9/00

CPC classification number: G06V10/16 ,  G06T5/50 ,  G06T7/11 ,  G06T9/00 ,  G06T2207/20221

Abstract: Methods and apparatus for tile-based stitching and encoding of images are disclosed. An example apparatus to stitch and encode images includes tile generation circuitry to generate first input tiles from a first image and second input tiles from a second image, the first image from a first camera and the second image from a second camera. The example apparatus also includes stitching circuitry to process the first input tiles and the second input tiles to convert the first input tiles into corresponding first stitched tiles and to convert the second input tiles into corresponding second stitched tiles. The example apparatus further includes encoding circuitry to encode the first stitched tiles and the second stitched tiles in parallel, wherein the tile generation circuitry is to generate the first input tiles and the second input tiles based on division information associated with the encoding circuitry.

公开(公告)号：US20240251089A1

公开(公告)日：2024-07-25

申请号：US18563330

申请日：2021-11-17

Applicant: Intel Corporation

Inventor： Fan He ,  Yunbiao Lin ,  Changliang Wang ,  Yue Heng

IPC: H04N19/164 ,  G06N3/092 ,  H04N19/172 ,  H04N19/196 ,  H04N19/42 ,  H04N19/80

CPC classification number: H04N19/164 ,  G06N3/092 ,  H04N19/172 ,  H04N19/197 ,  H04N19/42 ,  H04N19/80

Abstract: Techniques related to video coding with fast low-latency bitstream size control includes detecting outliers and determining a target bitstream size based on the outlier and reinforcement-learning.

公开(公告)号：US11514550B2

公开(公告)日：2022-11-29

申请号：US16916670

申请日：2020-06-30

Applicant: INTEL CORPORATION

Inventor： Yunbiao Lin ,  Changliang Wang ,  Satyanantha Ramagopal Musunuri ,  David Puffer ,  David J. Cowperthwaite ,  Bryan R. White ,  Balaji Vembu

IPC: G06T1/20 ,  G06T1/60 ,  G06F3/14 ,  G06F9/451 ,  G09G5/00 ,  G09G5/36 ,  G06F12/10 ,  G06F12/1009

Abstract: An apparatus and method for managing pipes and planes within a virtual graphics processing engine. For example, one embodiment of a graphics processing apparatus comprises: a graphics processor comprising one or more display pipes to render one or more display planes, each of the one or more display pipes comprising a set of graphics processing hardware resources for executing graphics commands and rendering graphics images in the one or more display planes; and pipe and plane management hardware logic to manage pipe and plane assignment, the pipe and plane management hardware logic to associate a first virtual machine (VM) with one or more virtual display planes and to maintain a mapping between the one or more virtual display planes and at least one physical display plane.

公开(公告)号：US20220150533A1

公开(公告)日：2022-05-12

申请号：US17526388

申请日：2021-11-15

Applicant: Intel Corporation

Inventor： Yunbiao Lin ,  Changliang Wang ,  Ce Wang ,  Yongfa Zhou ,  Bo Zhao ,  Ping Liu ,  Jianwei Yang ,  Zhan Lou ,  Yu Yang ,  Yating Wang ,  Wenyi Tang ,  Bo Qiu

IPC: H04N19/527 ,  H04N19/154 ,  H04N19/167 ,  H04N19/176 ,  H04N19/52 ,  H04N19/189

Abstract: An embodiment of an adaptive video encoder may include technology to determine headset-related information including at least one of focus-related information and motion-related information, and determine one or more video encode parameters based on the headset-related information. Other embodiments are disclosed and claimed.

公开(公告)号：US11322099B2

公开(公告)日：2022-05-03

申请号：US16939916

申请日：2020-07-27

Applicant: Intel Corporation

Inventor： Arthur J. Runyan ,  Richmond Hicks ,  Nausheen Ansari ,  Narayan Biswal ,  Ya-Ti Peng ,  Abhishek R. Appu ,  Wen-Fu Kao ,  Sang-Hee Lee ,  Joydeep Ray ,  Changliang Wang ,  Satyanarayana Avadhanam ,  Scott Janus ,  Gary Smith ,  Nilesh V. Shah ,  Keith W. Rowe ,  Robert J. Johnston

IPC: G09G3/34 ,  G09G3/36 ,  G09G5/10 ,  G09G5/14 ,  G09G5/38 ,  G06F3/147 ,  G02B27/01 ,  G09G5/00 ,  B60R1/00

Abstract: Often when there is a glare on a display screen the user may be able to mitigate the glare by tilting or otherwise moving the screen or changing their viewing position. However, when driving a car there are limited options for overcoming glares on the dashboard, especially when you are driving for a long distance in the same direction. Embodiments are directed to eliminating such glare. Other embodiments are related to mixed reality (MR) and filling in occluded areas.

公开(公告)号：US11289030B2

公开(公告)日：2022-03-29

申请号：US16939916

申请日：2020-07-27

Applicant: Intel Corporation

Inventor： Arthur J. Runyan ,  Richmond Hicks ,  Nausheen Ansari ,  Narayan Biswal ,  Ya-Ti Peng ,  Abhishek R. Appu ,  Wen-Fu Kao ,  Sang-Hee Lee ,  Joydeep Ray ,  Changliang Wang ,  Satyanarayana Avadhanam ,  Scott Janus ,  Gary Smith ,  Nilesh V. Shah ,  Keith W. Rowe ,  Robert J. Johnston

IPC: G09G3/34 ,  G09G3/36 ,  G09G5/10 ,  G09G5/14 ,  G09G5/38 ,  G06F3/147 ,  G02B27/01 ,  G09G5/00 ,  B60R1/00

Abstract: Often when there is a glare on a display screen the user may be able to mitigate the glare by tilting or otherwise moving the screen or changing their viewing position. However, when driving a car there are limited options for overcoming glares on the dashboard, especially when you are driving for a long distance in the same direction. Embodiments are directed to eliminating such glare. Other embodiments are related to mixed reality (MR) and filling in occluded areas.

公开(公告)号：US11069022B1

公开(公告)日：2021-07-20

申请号：US16728749

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： Changliang Wang ,  Penne Lee ,  Dmitry Ermilov

IPC: G06T1/20 ,  G09G5/36 ,  G06T9/00 ,  G06F15/80 ,  G06F9/38 ,  G06F9/30

Abstract: An apparatus and method for multi-adapter and/or multi-pass encoding on dual graphics processors. For example, one embodiment of a processor comprises: a central processor integrated on a first die, the central processor comprising a plurality of cores to execute instructions and process data; an first graphics processor integrated on the first die, the first graphics processor comprising media processing circuitry to perform one or more preliminary lookahead operations on video content to generate lookahead statistics; an interconnect to couple the first graphics processor to a lookahead buffer, the first graphics processor to transmit the lookahead statistics over the interconnect to the lookahead buffer; wherein the lookahead statistics are to be used by a second graphics processor to encode the video content to generate encoded video.

公开(公告)号：US20210150663A1

公开(公告)日：2021-05-20

申请号：US17095590

申请日：2020-11-11

Applicant: Intel Corporation

Inventor： Subramaniam Maiyuran ,  Durgaprasad Bilagi ,  Joydeep Ray ,  Scott Janus ,  Sanjeev Jahagirdar ,  Brent Insko ,  Lidong Xu ,  Abhishek R. Appu ,  James Holland ,  Vasanth Ranganathan ,  Nikos Kaburlasos ,  Altug Koker ,  Xinmin Tian ,  Guei-Yuan Lueh ,  Changliang Wang

IPC: G06T1/60 ,  G06T1/20 ,  G06N5/04 ,  G06F12/0802

Abstract: Embodiments described herein are generally directed to improvements relating to power, latency, bandwidth and/or performance issues relating to GPU processing/caching. According to one embodiment, a system includes a producer intellectual property (IP) (e.g., a media IP), a compute core (e.g., a GPU or an AI-specific core of the GPU), a streaming buffer logically interposed between the producer IP and the compute core. The producer IP is operable to consume data from memory and output results to the streaming buffer. The compute core is operable to perform AI inference processing based on data consumed from the streaming buffer and output AI inference processing results to the memory.

公开(公告)号：US10915996B2

公开(公告)日：2021-02-09

申请号：US16306315

申请日：2016-07-01

Applicant: INTEL CORPORATION

Inventor： Yunbiao Lin ,  Yadong Li ,  Changliang Wang ,  Gang Hu

IPC: G06T5/00 ,  G06T5/50 ,  G06T5/20

Abstract: Techniques are provided for enhancement of edges in image frames using depth information. A methodology implementing the techniques according to an embodiment includes receiving a color image frame and a depth map frame. The method also includes generating a sharpness mask to control the application of image sharpening to the color pixels. The sharpness mask is based on the value of depth pixels corresponding to the color pixels; and on properties of the depth camera that generated the color image frame, including depth of field, focal distance, and hyperfocal distance. The method further includes calculating sharpness strength for the color pixels. The sharpness strength is proportional to the value of the depth pixel corresponding to the color pixel. The method further includes applying a sharpening filter to the color image frame to enhance edge image features. The sharpening filter is based on the sharpness mask and the sharpness strength.

公开(公告)号：US10915608B2

公开(公告)日：2021-02-09

申请号：US16126060

申请日：2018-09-10

Applicant: Intel Corporation

Inventor： Balaji Vembu ,  Vidhya Krishnan ,  Sandeep Sodhi ,  Sreekanth Mavila ,  Altug Koker ,  Aditya Navale ,  Scott Janus ,  Changliang Wang

IPC: H04L9/00 ,  G06F21/12 ,  G06T15/00 ,  H04N21/254 ,  G06F9/48 ,  H04L9/08 ,  G06F21/60 ,  G06T1/20 ,  G06T1/60

Abstract: Apparatus and method for scalable content protection. For example, one embodiment of an apparatus comprises: cryptographic management circuitry to securely store one or more keys associated with one or more media apps/applications; a plurality of processing engines, each processing engine comprising circuitry to process media content of the one or more media apps/applications; and a scheduler to schedule processing of the media content by the processing engines; wherein the cryptographic management circuitry is to restore a first cryptographic state including a first key associated with a first media app/application and/or first media content responsive to a request to process the first media content on a first processing engine.