公开(公告)号：US20220189957A1

公开(公告)日：2022-06-16

申请号：US17117978

申请日：2020-12-10

Applicant: Intel Corporation

Inventor： Sarah Atanasov ,  Abhishek A. Sharma ,  Bernhard Sell ,  Chieh-Jen Ku ,  Elliot Tan ,  Hui Jae Yoo ,  Noriyuki Sato ,  Travis W. Lajoie ,  Van H. Le

IPC: H01L27/108 ,  G11C11/402 ,  H01L29/24

Abstract: Disclosed herein are transistors, memory cells, and arrangements thereof. For example, in some embodiments, an integrated circuit (IC) structure may include a plurality of transistors, wherein the transistors are distributed in a hexagonally packed arrangement. In another example, in some embodiments, an IC structure may include a memory cell including an axially symmetric transistor coupled to an axially symmetric capacitor, wherein the axis of the transistor is aligned with the axis of the capacitor.

公开(公告)号：US11973105B2

公开(公告)日：2024-04-30

申请号：US16145111

申请日：2018-09-27

Applicant: Intel Corporation

Inventor： Chieh-Jen Ku ,  Bernhard Sell ,  Leif Paulson ,  Kinyip Phoa ,  Shi Liu

IPC: H01L23/522 ,  H01L27/01 ,  H01L49/02

CPC classification number: H01L28/24 ,  H01L23/5228 ,  H01L27/016

Abstract: An integrated circuit structure comprises at least one metal gate formed in a first dielectric layer, the at least one metal gate comprising a workfunction layer and the gate oxide layer along sidewalls of the first dielectric layer. A field effect (FE) dielectric layer dielectric layer is above the first dielectric layer of the at least one metal gate. A precision resistor comprising a thin-film metallic material is formed on the FE dielectric layer above the at least one metal gate and extending laterally over the at least one metal gate.

公开(公告)号：US11908911B2

公开(公告)日：2024-02-20

申请号：US16414481

申请日：2019-05-16

Applicant: Intel Corporation

Inventor： Chieh-Jen Ku ,  Bernhard Sell ,  Pei-Hua Wang

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/45 ,  H01L29/786

CPC classification number: H01L29/42356 ,  H01L29/45 ,  H01L29/66742 ,  H01L29/786

Abstract: A device is disclosed. The device includes a source contact in a source contact trench and a drain contact in a drain contact trench, a channel under the source contact and the drain contact, a first spacing layer on a bottom of the source contact trench and a second spacing layer on a bottom of the drain contact trench. The first spacing layer and the second spacing layer are on the surface of the channel. The device also includes a gate electrode below the channel and a dielectric above the gate electrode and underneath the channel.

公开(公告)号：US11832438B2

公开(公告)日：2023-11-28

申请号：US16457634

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Travis W. Lajoie ,  Abhishek A. Sharma ,  Van H. Le ,  Chieh-Jen Ku ,  Pei-Hua Wang ,  Jack T. Kavalieros ,  Bernhard Sell ,  Tahir Ghani ,  Gregory George ,  Akash Garg ,  Allen B. Gardiner ,  Shem Ogadhoh ,  Juan G. Alzate Vinasco ,  Umut Arslan ,  Fatih Hamzaoglu ,  Nikhil Mehta ,  Jared Stoeger ,  Yu-Wen Huang ,  Shu Zhou

IPC: H10B12/00 ,  H01L27/12 ,  H01L49/02

CPC classification number: H10B12/315 ,  H01L27/124 ,  H01L27/1218 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/1248 ,  H01L27/1255 ,  H01L28/55 ,  H01L28/65 ,  H01L28/82 ,  H10B12/0335 ,  H10B12/312

Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate. A first capacitor includes a first top plate and a first bottom plate above the substrate. The first top plate is coupled to a first metal electrode within an inter-level dielectric (ILD) layer to access the first capacitor. A second capacitor includes a second top plate and a second bottom plate, where the second top plate is coupled to a second metal electrode within the ILD layer to access the second capacitor. The second metal electrode is disjoint from the first metal electrode. The first capacitor is accessed through the first metal electrode without accessing the second capacitor through the second metal electrode. Other embodiments may be described and/or claimed.

公开(公告)号：US11758711B2

公开(公告)日：2023-09-12

申请号：US17696945

申请日：2022-03-17

Applicant: Intel Corporation

Inventor： Yih Wang ,  Abhishek A. Sharma ,  Tahir Ghani ,  Allen B. Gardiner ,  Travis W. Lajoie ,  Pei-Hua Wang ,  Chieh-Jen Ku ,  Bernhard Sell ,  Juan G. Alzate-Vinasco ,  Blake C. Lin

IPC: H01L27/108 ,  H01L23/522 ,  H01L23/528 ,  H10B12/00 ,  H01L27/06 ,  H01L27/12

CPC classification number: H10B12/315 ,  H01L23/528 ,  H01L23/5223 ,  H01L23/5226 ,  H01L27/0605 ,  H01L27/124 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/1262 ,  H10B12/0335 ,  H10B12/05 ,  H10B12/482 ,  H10B12/488 ,  H10B12/50

Abstract: Described herein are embedded dynamic random-access memory (eDRAM) memory cells and arrays, as well as corresponding methods and devices. An exemplary eDRAM memory array implements a memory cell that uses a thin-film transistor (TFT) as a selector transistor. One source/drain (S/D) electrode of the TFT is coupled to a capacitor for storing a memory state of the cell, while the other S/D electrode is coupled to a bitline. The bitline may be a shallow bitline in that a thickness of the bitline may be smaller than a thickness of one or more metal interconnects provided in the same metal layer as the bitline but used for providing electrical connectivity for components outside of the memory array. Such a bitline may be formed in a separate process than said one or more metal interconnects. In an embodiment, the memory cells may be formed in a back end of line process.

公开(公告)号：US11683929B2

公开(公告)日：2023-06-20

申请号：US17840186

申请日：2022-06-14

Applicant: Intel Corporation

Inventor： Travis W. Lajoie ,  Abhishek Sharma ,  Van H. Le ,  Chieh-Jen Ku ,  Pei-Hua Wang ,  Jack T. Kavalieros ,  Bernhard Sell ,  Tahir Ghani ,  Juan Alzate Vinasco

IPC: H01L21/82 ,  H10B12/00 ,  H01L29/786 ,  H01L29/66 ,  H01L29/49 ,  H01L21/311 ,  H01L21/822 ,  H01L21/8234

CPC classification number: H10B12/33 ,  H01L21/31111 ,  H01L21/8221 ,  H01L21/823487 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78642 ,  H01L29/78663 ,  H01L29/78672 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78693 ,  H01L29/78696 ,  H10B12/036 ,  H10B12/05

Abstract: Embodiments herein describe techniques for a semiconductor device including a capacitor and a transistor above the capacitor. A contact electrode may be shared between the capacitor and the transistor. The capacitor includes a first plate above a substrate, and the shared contact electrode above the first plate and separated from the first plate by a capacitor dielectric layer, where the shared contact electrode acts as a second plate for the capacitor. The transistor includes a gate electrode above the substrate and above the capacitor; a channel layer separated from the gate electrode by a gate dielectric layer, and in contact with the shared contact electrode; and a source electrode above the channel layer, separated from the gate electrode by the gate dielectric layer, and in contact with the channel layer. The shared contact electrode acts as a drain electrode of the transistor. Other embodiments may be described and/or claimed.

公开(公告)号：US11563107B2

公开(公告)日：2023-01-24

申请号：US16361881

申请日：2019-03-22

Applicant: Intel Corporation

Inventor： Chieh-Jen Ku ,  Bernhard Sell ,  Pei-Hua Wang ,  Nikhil Mehta ,  Shu Zhou ,  Jared Stoeger ,  Allen B. Gardiner ,  Akash Garg ,  Shem Ogadhoh ,  Vinaykumar Hadagali ,  Travis W. Lajoie

IPC: H01L29/66 ,  H01L27/108 ,  H01L29/786

Abstract: An integrated circuit structure comprises one or more backend-of-line (BEOL) interconnects formed over a first ILD layer. An etch stop layer is over the one or more BEOL interconnects, the etch stop layer having a plurality of vias that are in contact with the one or more BEOL interconnects. An array of BEOL thin-film-transistors (TFTs) is over the etch stop layer, wherein adjacent ones of the BEOL TFTs are separated by isolation trench regions. The TFTs are aligned with at least one of the plurality of vias to connect to the one or more BEOL interconnects, wherein each of the BEOL TFTs comprise a bottom gate electrode, a gate dielectric layer over the bottom gate electrode, and an oxide-based semiconductor channel layer over the bottom gate electrode having source and drain regions therein. Contacts are formed over the source and drain regions of each of BEOL TFTs, wherein the contacts have a critical dimension of 35 nm or less, and wherein the BEOL TFTs have an absence of diluted hydro-fluoride (DHF).

公开(公告)号：US11121073B2

公开(公告)日：2021-09-14

申请号：US15943565

申请日：2018-04-02

Applicant: Intel Corporation

Inventor： Travis Lajoie ,  Abhishek Sharma ,  Juan Alzate-Vinasco ,  Chieh-Jen Ku ,  Shem Ogadhoh ,  Allen Gardiner ,  Blake Lin ,  Yih Wang ,  Pei-Hua Wang ,  Jack T. Kavalieros ,  Bernhard Sell ,  Tahir Ghani

IPC: H01L23/522 ,  H01L49/02 ,  H01L27/108 ,  H01L23/532

Abstract: An interconnect structure is disclosed. The interconnect structure includes a first metal interconnect in a bottom dielectric layer, a via that extends through a top dielectric layer, a metal plate, an intermediate dielectric layer, and an etch stop layer, and a metal in the via to extend through the top dielectric layer, the metal plate, the intermediate dielectric layer and the etch stop layer to the top surface of the first metal interconnect. The metal plate is coupled to an MIM capacitor that is parallel to the via. The second metal interconnect is on top of the metal in the via.

公开(公告)号：US12080643B2

公开(公告)日：2024-09-03

申请号：US16583691

申请日：2019-09-26

Applicant: Intel Corporation

Inventor： Travis W. Lajoie ,  Abhishek A. Sharma ,  Juan G. Alzate Vinasco ,  Chieh-Jen Ku ,  Shem O. Ogadhoh ,  Allen B. Gardiner ,  Blake C. Lin ,  Yih Wang ,  Pei-Hua Wang ,  Jack T. Kavalieros ,  Bernhard Sell ,  Tahir Ghani

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76829 ,  H01L23/5223 ,  H01L23/5226

Abstract: Integrated circuit structures having differentiated interconnect lines in a same dielectric layer, and methods of fabricating integrated circuit structures having differentiated interconnect lines in a same dielectric layer, are described. In an example, an integrated circuit structure includes an inter-layer dielectric (ILD) layer above a substrate. A plurality of conductive interconnect lines is in the ILD layer. The plurality of conductive interconnect lines includes a first interconnect line having a first height, and a second interconnect line immediately laterally adjacent to but spaced apart from the first interconnect line, the second interconnect line having a second height less than the first height.

公开(公告)号：US20240234579A1

公开(公告)日：2024-07-11

申请号：US18444520

申请日：2024-02-16

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Arnab Sen Gupta ,  Travis W. LaJoie ,  Sarah Atanasov ,  Chieh-Jen Ku ,  Bernhard Sell ,  Noriyuki Sato ,  Van Le ,  Matthew Metz ,  Hui Jae Yoo ,  Pei-Hua Wang

IPC: H01L29/786 ,  H01L29/66 ,  H10B61/00 ,  H10B63/00

CPC classification number: H01L29/7869 ,  H01L29/66969 ,  H10B61/22 ,  H10B63/30

Abstract: A thin film transistor (TFT) structure includes a gate electrode, a gate dielectric layer on the gate electrode, a channel layer including a semiconductor material with a first polarity on the gate dielectric layer. The TFT structure also includes a multi-layer material stack on the channel layer, opposite the gate dielectric layer, an interlayer dielectric (ILD) material over the multi-layer material stack and beyond a sidewall of the channel layer. The TFT structure further includes source and drain contacts through the interlayer dielectric material, and in contact with the channel layer, where the multi-layer material stack includes a barrier layer including oxygen and a metal in contact with the channel layer, where the barrier layer has a second polarity. A sealant layer is in contact with the barrier layer, where the sealant layer and the ILD have a different composition.