公开(公告)号：US20220326757A1

公开(公告)日：2022-10-13

申请号：US17853442

申请日：2022-06-29

Applicant: Intel Corporation

Inventor： Jaroslaw J. Sydir ,  Bin Li ,  Christopher MacNamara ,  David Hunt

IPC: G06F1/3234 ,  G06F1/3296 ,  G06F1/329

Abstract: The present disclosure is related to power control mechanisms for workload processing systems, and in particular, multi-scale power control technologies that can be used to reduce the overhead of workload processing systems. The disclosed power control mechanisms operate on multiple timescales including a slow timescale and a fast timescale. Separate control loops (or governors) are used for the slow and fast timescales where each control loop includes its own trigger mechanisms and configurable operational policies. The operational policies for slow timescale control loop can be trained separately using various machine learning techniques while the operational policies for the fast timescale control loop can be simple and reactive heuristics.

公开(公告)号：US11431565B2

公开(公告)日：2022-08-30

申请号：US16160176

申请日：2018-10-15

Applicant: Intel Corporation

Inventor： Mohammad Abdul Awal ,  Jasvinder Singh ,  Reshma Pattan ,  David Hunt ,  Declan Doherty ,  Chris Macnamara

IPC: H04L41/0816 ,  H04L49/90 ,  H04L43/16 ,  H04L43/0894 ,  H04L49/00 ,  H04L43/10

Abstract: Examples include techniques for monitoring a data packet transfer rate at an interface queue, and based at least in part on a comparison of the data packet transfer rate to a threshold, assigning the interface queue from a core of a first class to a core of a second class or assigning the interface queue from a core of the second class to a core of the first class.

公开(公告)号：US20210136680A1

公开(公告)日：2021-05-06

申请号：US17119698

申请日：2020-12-11

Applicant: Intel Corporation

Inventor： John J. Browne ,  Chris M. MacNamara ,  David Hunt ,  Amruta Misra ,  Tomasz Kantecki ,  Shobhi Jain ,  Liang Ma

IPC: H04W52/02 ,  H04L12/24

Abstract: A system comprising an interface to access a network slice power consumption parameter for a network slice comprising a logical network between two endpoints through a plurality of physical computing platforms; and a controller comprising circuitry, the controller to specify operating parameters for a plurality of hardware resources of a first physical computing platform in accordance with the network slice power consumption parameter.

公开(公告)号：US11630693B2

公开(公告)日：2023-04-18

申请号：US15951650

申请日：2018-04-12

Applicant: Intel Corporation

Inventor： John Browne ,  Chris MacNamara ,  Tomasz Kantecki ,  Peter McCarthy ,  Liang Ma ,  Mairtin O'Loingsigh ,  Rory Sexton ,  John Griffin ,  Nemanja Marjanovic ,  David Hunt

IPC: G06F9/46 ,  G06F9/48 ,  H04L47/24 ,  G06F1/329 ,  H04L9/40 ,  H04L47/6275 ,  G06F1/3209 ,  G06F1/3296 ,  G06F1/3234 ,  H04L47/625 ,  G06F9/50 ,  G06F21/60

Abstract: Technologies for power-aware scheduling include a computing device that receives network packets. The computing device classifies the network packets by priority level and then assigns each network packet to a performance group bin. The packets are assigned based on priority level and other performance criteria. The computing device schedules the network packets assigned to each performance group for processing by a processing engine such as a processor core. Network packets assigned to performance groups having a high priority level are scheduled for processing by processing engines with a high performance level. The computing device may select performance levels for processing engines based on processing workload of the network packets. The computing device may control the performance level of the processing engines, for example by controlling the frequency of processor cores. The processing workload may include packet encryption. Other embodiments are described and claimed.

公开(公告)号：US20210182194A1

公开(公告)日：2021-06-17

申请号：US17185648

申请日：2021-02-25

Applicant: Intel Corporation

Inventor： John J. Browne ,  Adrian Boczkowski ,  Marcel D. Cornu ,  David Hunt ,  Shobhi Jain ,  Tomasz Kantecki ,  Liang Ma ,  Chris M. MacNamara ,  Amruta Misra ,  Terence Nally

IPC: G06F12/0811 ,  G06F12/0871 ,  G06F9/50 ,  G06F11/07

Abstract: A performance monitor provides cache miss stall and memory bandwidth usage metric samples to a resource exhaustion detector. The detector can detect the presence of last-level cache and memory bandwidth exhaustion conditions based on the metric samples. If cache miss stalls and memory bandwidth usage are both trending up, the detector reports a memory bandwidth exhaustion condition to a resource controller. If cache miss stalls are trending up and memory bandwidth usage is trending down, the detector reports a last-level cache exhaustion condition to the resource controller. The resource controller can allocate additional last-level cache or memory bandwidth to the processor unit to remediate the resource exhaustion condition. If bandwidth-related metric samples indicate that a processor unit may be overloaded due to receiving high bandwidth traffic, the resource controller can take a traffic rebalancing remedial action.

公开(公告)号：US20190041957A1

公开(公告)日：2019-02-07

申请号：US15951391

申请日：2018-04-12

Applicant: Intel Corporation

Inventor： David Hunt ,  Niall Power ,  Kevin Devey ,  Changzheng Wei ,  Bruce Richardson ,  Eliezer Tamir ,  Andrew Cunningham ,  Chris MacNamara ,  Nemanja Marjanovic ,  Rory Sexton ,  John Browne

IPC: G06F1/32

Abstract: Technologies for providing efficient detection of idle poll loops include a compute device. The compute device has a compute engine that includes a plurality of cores and a memory. The compute engine is to determine a ratio of unsuccessful operations to successful operations over a predefined time period of a core of the plurality cores that is assigned to continually poll, within the predefined time period, a memory address for a change in status and determine whether the determined ratio satisfies a reference ratio of unsuccessful operations to successful operations. The reference ratio is indicative of a change in the operation of the assigned core. The compute engine is further to selectively increase or decrease a power usage of the assigned core as a function of whether the determined ratio satisfies the reference ratio. Other embodiments are also described and claimed.