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公开(公告)号：US20180300932A1
公开(公告)日：2018-10-18
申请号：US15489139
申请日：2017-04-17
Applicant: Intel Corporation
Inventor： Atsuo Kuwahara , Deepak S. Vembar , Chandrasekaran Sakthivel , Radhakrishnan Venkataraman , Brent E. Insko , Anupreet S. Kalra , Hugues Labbe , Abhishek R. Appu , Ankur N. Shah , Joydeep Ray , Elmoustapha Ould-Ahmed-Vall , Prasoonkumar Surti , Murali Ramadoss
IPC: G06T15/00
Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The graphics subsystem may include a first graphics engine to process a graphics workload, and a second graphics engine to offload at least a portion of the graphics workload from the first graphics engine. The second graphics engine may include a low precision compute engine. The system may further include a wearable display housing the second graphics engine. Other embodiments are disclosed and claimed.
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公开(公告)号：US20180293760A1
公开(公告)日：2018-10-11
申请号：US15483701
申请日：2017-04-10
Applicant: Intel Corporation
Inventor： Karthik Vaidyanathan , Prasoonkumar Surti , Hugues Labbe , Atsuo Kuwahara , Sameer Kp , Jonathan Kennedy , Murali Ramadoss , Michael Apodaca , Abhishek Venkatesh
CPC classification number: G06T11/001 , G06T1/20 , G06T1/60 , G06T15/005 , G06T2210/52
Abstract: Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.
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公开(公告)号：US12288287B2
公开(公告)日：2025-04-29
申请号：US18436688
申请日：2024-02-08
Applicant: Intel Corporation
Inventor： Atsuo Kuwahara , Deepak S. Vembar , Chandrasekaran Sakthivel , Radhakrishnan Venkataraman , Brent E. Insko , Anupreet S. Kalra , Hugues Labbe , Abhishek R. Appu , Ankur N. Shah , Joydeep Ray , Elmoustapha Ould-Ahmed-Vall , Prasoonkumar Surti , Murali Ramadoss
Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The graphics subsystem may include a first graphics engine to process a graphics workload, and a second graphics engine to offload at least a portion of the graphics workload from the first graphics engine. The second graphics engine may include a low precision compute engine. The system may further include a wearable display housing the second graphics engine. Other embodiments are disclosed and claimed.
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公开(公告)号：US11461959B2
公开(公告)日：2022-10-04
申请号：US16865587
申请日：2020-05-04
Applicant: Intel Corporation
Inventor： Prasoonkumar Surti , Karthik Vaidyanathan , Atsuo Kuwahara , Hugues Labbe , Sameer Kp , Jonathan Kennedy , Abhishek R. Appu , Jeffery S. Boles , Balaji Vembu , Michael Apodaca , Slawomir Grajewski , Gabor Liktor , David M. Cimini , Andrew T. Lauritzen , Travis T. Schluessler , Murali Ramadoss , Abhishek Venkatesh , Joydeep Ray , Kai Xiao , Ankur N. Shah , Altug Koker
Abstract: The systems, apparatuses and methods may provide a way to adaptively process and aggressively cull geometry data. Systems, apparatuses and methods may provide for processing, by a positional only shading pipeline (POSH), geometry data including surface triangles for a digital representation of a scene. More particularly, systems, apparatuses and methods may provide a way to identify surface triangles in one or more exclusion zones and non-exclusion zones, and cull surface triangles in one or more exclusion zones.
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公开(公告)号：US20220206990A1
公开(公告)日：2022-06-30
申请号：US17561427
申请日：2021-12-23
Applicant: Intel Corporation
Inventor： Altug Koker , Prasoonkumar Surti , David Puffer , Subramaniam Maiyuran , Guei-Yuan Lueh , Abhishek R. Appu , Joydeep Ray , Balaji Vembu , Tomer Bar-On , Andrew T. Lauritzen , Hugues Labbe , John G. Gierach , Gabor Liktor
Abstract: In an example, an apparatus comprises a plurality of execution units, and a first memory communicatively couple to the plurality of execution units, wherein the first shared memory is shared by the plurality of execution units and a copy engine to copy context state data from at least a first of the plurality of execution units to the first shared memory. Other embodiments are also disclosed and claimed.
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Patent Agency Ranking
16.发明授权公开(公告)号：US11182296B2
公开(公告)日：2021-11-23
申请号：US16566188
申请日：2019-09-10
Applicant: Intel Corporation
Inventor： Andrew T. Lauritzen , Gabor Liktor , Tomer Bar-On , Hugues Labbe , John G. Gierach , Joydeep Ray , Travis T. Schluessler , John H. Feit , Nikos Kaburlasos , Jacek Kwiatkowski , Abhishek R. Appu , Balaji Vembu , Altug Koker
IPC: G06F12/0862 , G06F9/30 , G06F12/0875 , G06F9/38 , G06F12/0811 , G06F12/0855 , G06T1/20
Abstract: Systems, apparatuses and methods may provide a way to track graphics pipeline operations. More particularly, the systems, apparatuses and methods may provide a way to track operation dependencies between graphics pipeline operations for blocks of pixel samples and stall one or more of the pipeline operations based on the operation dependencies. The systems, apparatuses and methods may further provide cache pre-fetch hardware to monitor processing of blocks of pixel samples and fetch a next block of the pixel samples from the memory into a cache before completion of processing a current block of pixel samples based on one or more of the pipeline operations or a surface state of one or more regions of a screen space.
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公开(公告)号：US20210350597A1
公开(公告)日：2021-11-11
申请号：US17194819
申请日：2021-03-08
Applicant: Intel Corporation
Inventor： Deepak S. Vembar , Atsuo Kuwahara , Chandrasekaran Sakthivel , Radhakrishnan Venkataraman , Brent E. Insko , Anupreet S. Kalra , Hugues Labbe , Abhishek R. Appu , Ankur N. Shah , Joydeep Ray , ElMoustapha Ould-Ahmed-Vall , James M. Holland
IPC: G06T11/60 , G06T9/00 , H04N19/124 , H04N19/167 , H04N19/17 , H04N19/436 , H04N19/503
Abstract: An embodiment of a graphics apparatus may include a focus identifier to identify a focus area, and a color compressor to selectively compress color data based on the identified focus area. Another embodiment of a graphics apparatus may include a motion detector to detect motion of a real object, a motion predictor to predict a motion of the real object, and an object placer to place a virtual object relative to the real object based on the predicted motion of the real object. Another embodiment of a graphics apparatus may include a frame divider to divide a frame into viewports, a viewport prioritizer to prioritize the viewports, a renderer to render a viewport of the frame in order in accordance with the viewport priorities, and a viewport transmitter to transmit a completed rendered viewport. Other embodiments are disclosed and claimed.
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公开(公告)号：US10943379B2
公开(公告)日：2021-03-09
申请号：US16533920
申请日：2019-08-07
Applicant: Intel Corporation
Inventor： Deepak S. Vembar , Atsuo Kuwahara , Chandrasekaran Sakthivel , Radhakrishnan Venkataraman , Brent E. Insko , Anupreet S. Kalra , Hugues Labbe , Abhishek R. Appu , Ankur N. Shah , Joydeep Ray , ElMoustapha Ould-Ahmed-Vall , James M. Holland
IPC: G09G5/00 , G06T11/60 , G06T9/00 , H04N19/124 , H04N19/167 , H04N19/17 , H04N19/436 , H04N19/503
Abstract: An embodiment of a graphics apparatus may include a focus identifier to identify a focus area, and a color compressor to selectively compress color data based on the identified focus area. Another embodiment of a graphics apparatus may include a motion detector to detect motion of a real object, a motion predictor to predict a motion of the real object, and an object placer to place a virtual object relative to the real object based on the predicted motion of the real object. Another embodiment of a graphics apparatus may include a frame divider to divide a frame into viewports, a viewport prioritizer to prioritize the viewports, a renderer to render a viewport of the frame in order in accordance with the viewport priorities, and a viewport transmitter to transmit a completed rendered viewport. Other embodiments are disclosed and claimed.
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公开(公告)号：US20210035270A1
公开(公告)日：2021-02-04
申请号：US16929787
申请日：2020-07-15
Applicant: Intel Corporation
Inventor： Tomer Bar-On , Hugues Labbe , Adam T. Lake , Kai Xiao , Ankur N. Shah , Johannes Guenther , Abhishek R. Appu , Joydeep Ray , Deepak S. Vembar , ElMoustapha Ould-Ahmed-Vall
Abstract: Systems, apparatuses and methods may provide for technology that identifies, at an image post-processor, unresolved surface data and identifies, at the image post-processor, control data associated with the unresolved surface data. Additionally, the technology may resolve, at the image post-processor, the unresolved surface data and the control data into a final image.
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公开(公告)号：US10893299B2
公开(公告)日：2021-01-12
申请号：US16050391
申请日：2018-07-31
Applicant: Intel Corporation
Inventor： Jill Boyce , Scott Janus , Itay Kaufman , Archie Sharma , Stanley Baran , Michael Apodaca , Prasoonkumar Surti , Srikanth Potluri , Barnan Das , Hugues Labbe , Jong Dae Oh , Gokcen Cilingir , Maria Bortman , Tzach Ashkenazi , Jonathan Distler , Atul Divekar , Mayuresh M. Varerkar , Narayan Biswal , Nilesh V. Shah , Atsuo Kuwahara , Kai Xiao , Jason Tanner , Jeffrey Tripp
Abstract: An apparatus to facilitate processing video bit stream data is disclosed. The apparatus includes one or more processors to encode surface normals data with point cloud geometry data included in the video bit stream data for reconstruction of objects within the video bit stream data based on the surface normals data and a memory communicatively coupled to the one or more processors.
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