公开(公告)号：US09009413B2

公开(公告)日：2015-04-14

申请号：US13724848

申请日：2012-12-21

Applicant: Intel Corporation

Inventor： Varun K. Mohandru ,  Fernando Latorre ,  Niranjan L. Cooray ,  Pedro Lopez ,  Naveen Neelakantam ,  Li-Gao Zei ,  Rami May ,  Jaroslaw Topp ,  Thomas Gaertner

IPC: G06F12/08 ,  G11C7/10 ,  G06F12/10

CPC classification number: G11C7/1072 ,  G06F12/0804 ,  G06F12/0891 ,  G06F12/1036

Abstract: A processor includes a processor core including an execution unit to execute instructions, and a cache memory. The cache memory includes a controller to update each of a plurality of stale indicators in response to a lazy flush instruction. Each stale indicator is associated with respective data, and each updated stale indicator is to indicate that the respective data is stale. The cache memory also includes a plurality of cache lines. Each cache line is to store corresponding data and a foreground tag that includes a respective virtual address associated with the corresponding data, and that includes the associated stale indicator. Other embodiments are described as claimed.

Abstract translation: 处理器包括处理器核心，其包括执行指令的执行单元和高速缓冲存储器。 高速缓冲存储器包括控制器，以响应于惰性冲洗指令来更新多个陈旧指示器中的每一个。 每个陈旧的指示符与相应的数据相关联，每个更新的陈旧指示符指示相应的数据是否过时。 高速缓冲存储器还包括多条高速缓存行。 每个高速缓存行将存储对应的数据和前景标签，其包括与对应的数据相关联的相应的虚拟地址，并且其包括相关联的陈旧指示符。 其他实施例被描述为所要求保护的。