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    Power efficient level one data cache access with pre-validated tags
    2.
    发明授权
    Power efficient level one data cache access with pre-validated tags 有权
    高效的一级数据缓存访问与预先验证的标签

    公开(公告)号：US09311239B2

    公开(公告)日：2016-04-12

    申请号：US13976313

    申请日：2013-03-14

    Applicant: Intel Corporation

    Inventor： Niranjan Cooray ,  Steffen Kosinski ,  Rami May ,  Doron Gershon ,  Jaroslaw Topp ,  Varun Mohandru

    IPC: G06F12/00 ,  G06F12/08 ,  G06F12/10

    CPC classification number: G06F12/0811 ,  G06F12/0864 ,  G06F12/10 ,  G06F12/1027 ,  G06F12/1045 ,  G06F2212/283 ,  G06F2212/6032 ,  G06F2212/65 ,  G06F2212/681 ,  Y02D10/13

    Abstract: A system and method to implement a tag structure for a cache memory that includes a multi-way, set-associative translation lookaside buffer. The tag structure may store vectors in an L1 tag array to enable an L1 tag lookup that has fewer bits per entry and consumes less power. The vectors may identify entries in a translation lookaside buffer tag array. When a virtual memory address associated with a memory access instruction hits in the translation lookaside buffer, the translation lookaside buffer may generate a vector identifying the set and the way of the translation lookaside buffer entry that matched. This vector may then be compared to a group of vectors stored in a set of the L1 tag arrays to determine whether the virtual memory address hits in the L1 cache.

    Abstract translation: 一种用于实现高速缓冲存储器的标签结构的系统和方法，其包括多路组合关联翻译后备缓冲器。 标签结构可以将向量存储在L1标签阵列中，以便能够进行每个条目具有较少位的L1标签查找并消耗更少的功率。 向量可以标识翻译后备缓冲器标签阵列中的条目。 当与存储器访问指令相关联的虚拟存储器地址在翻译后备缓冲器中时，翻译后备缓冲器可以生成标识集合的向量和匹配的翻译后备缓冲器条目的方式。 然后将该向量与存储在一组L1标签阵列中的一组矢量进行比较，以确定虚拟存储器地址是否在L1高速缓存中命中。

    Power Efficient Level One Data Cache Access With Pre-Validated Tags
    3.
    发明申请
    Power Efficient Level One Data Cache Access With Pre-Validated Tags 有权
    具有预验证标签的高效一级数据缓存访问

    公开(公告)号：US20150220436A1

    公开(公告)日：2015-08-06

    申请号：US13976313

    申请日：2013-03-14

    Applicant: Intel Corporation

    Inventor： Niranjan Cooray ,  Steffen Kosinski ,  Rami May ,  Doron Gershon ,  Jaroslaw Topp ,  Varun Mohandru

    IPC: G06F12/08 ,  G06F12/10

    CPC classification number: G06F12/0811 ,  G06F12/0864 ,  G06F12/10 ,  G06F12/1027 ,  G06F12/1045 ,  G06F2212/283 ,  G06F2212/6032 ,  G06F2212/65 ,  G06F2212/681 ,  Y02D10/13

    Abstract: A system and method to implement a tag structure for a cache memory that includes a multi-way, set-associative translation lookaside buffer. The tag structure may store vectors in an L1 tag array to enable an L1 tag lookup that has fewer bits per entry and consumes less power. The vectors may identify entries in a translation lookaside buffer tag array. When a virtual memory address associated with a memory access instruction hits in the translation lookaside buffer, the translation lookaside buffer may generate a vector identifying the set and the way of the translation lookaside buffer entry that matched. This vector may then be compared to a group of vectors stored in a set of the L1 tag arrays to determine whether the virtual memory address hits in the L1 cache.

    Abstract translation: 一种用于实现高速缓冲存储器的标签结构的系统和方法，其包括多路组合关联翻译后备缓冲器。 标签结构可以将向量存储在L1标签阵列中，以便能够进行每个条目具有较少位的L1标签查找并消耗更少的功率。 向量可以标识翻译后备缓冲器标签阵列中的条目。 当与存储器访问指令相关联的虚拟存储器地址在翻译后备缓冲器中时，翻译后备缓冲器可以生成标识集合的向量和匹配的翻译后备缓冲器条目的方式。 然后将该向量与存储在一组L1标签阵列中的一组矢量进行比较，以确定虚拟存储器地址是否在L1高速缓存中命中。

    INSTRUCTION AND LOGIC FOR SUPPORT OF CODE MODIFICATION IN TRANSLATION LOOKASIDE BUFFERS
    5.
    发明申请
    INSTRUCTION AND LOGIC FOR SUPPORT OF CODE MODIFICATION IN TRANSLATION LOOKASIDE BUFFERS 有权
    用于支持翻译LOOKASIDE BUFFERS中的代码修改的指导和逻辑

    公开(公告)号：US20160085685A1

    公开(公告)日：2016-03-24

    申请号：US14494781

    申请日：2014-09-24

    Applicant: Intel Corporation

    Inventor： Jaroslaw Topp ,  Niranjan L. Cooray ,  Fernando LaTorre

    IPC: G06F12/10 ,  G06F9/30

    CPC classification number: G06F12/1027 ,  G06F9/30003 ,  G06F9/30181 ,  G06F9/30185 ,  G06F9/3877 ,  G06F9/3887 ,  G06F12/0815 ,  G06F12/0888 ,  G06F12/1081 ,  G06F2212/1016 ,  G06F2212/30 ,  G06F2212/302 ,  G06F2212/50 ,  G06F2212/68

    Abstract: A processor includes a core with logic to execute a translated instruction. The translated instruction is translated from an instruction stored in a memory location. The processor further includes a translation lookaside buffer including logic to store translation indicators from a physical map. Each translation indicator indicates whether a corresponding memory location includes translated code to be protected. The processor further includes a translation indicator agent including logic to determine whether the buffer indicates whether the memory location has been modified subsequent to translation of the instruction.

    Abstract translation: 处理器包括具有执行翻译指令的逻辑的核心。 转换后的指令从存储在存储单元中的指令转换。 处理器还包括翻译后备缓冲器，其包括用于存储来自物理图的转换指示符的逻辑。 每个翻译指示符指示对应的存储器位置是否包括要保护的翻译代码。 处理器还包括翻译指示剂代理，其包括用于确定缓冲器是否指示在指令的翻译之后是否已经修改了存储器位置的逻辑。

    Two-level cache locking mechanism
    7.
    发明授权
    Two-level cache locking mechanism 有权
    两级缓存锁定机制

    公开(公告)号：US09558121B2

    公开(公告)日：2017-01-31

    申请号：US13729840

    申请日：2012-12-28

    Applicant: INTEL CORPORATION

    Inventor： Li-Gao Zei ,  Fernando Latorre ,  Steffen Kosinski ,  Jaroslaw Topp ,  Varun Mohandru ,  Lutz Naethke

    IPC: G06F12/00 ,  G06F12/08 ,  G06F12/10

    CPC classification number: G06F12/0846 ,  G06F12/0864 ,  G06F12/1063

    Abstract: A virtually tagged cache may be configured to index virtual address entries in the cache into lockable sets based on a page offset value. When a memory operation misses on the virtually tagged cache, only the one set of virtual address entries with the same page offset may be locked. Thereafter, this general lock may be released and only an address stored in the physical tag array matching the physical address and a virtual address in the virtual tag array corresponding to the matching address stored in the physical tag array may be locked to reduce the amount and duration of locked addresses. The machine may be stalled only if a particular memory address request hits and/or tries to access one or more entries in a locked set. Devices, systems, methods, and computer readable media are provided.

    Abstract translation: 虚拟标记的高速缓存可以被配置为基于页面偏移值将高速缓存中的虚拟地址条目索引到可锁定集合。 当内存操作错过虚拟标记的缓存时，只有一组具有相同页偏移量的虚拟地址条目可能被锁定。 此后，可以解除该通用锁定，并且仅锁定与物理地址匹配的物理标签阵列中存储的地址和与物理标签阵列中存储的匹配地址相对应的虚拟标签阵列中的虚拟地址，以减少数量和 锁定地址的持续时间。 只有当特定的存储器地址请求命中和/或尝试访问锁定集中的一个或多个条目时，才可能停止该机器。 提供了设备，系统，方法和计算机可读介质。

    APPARATUSES AND METHODS TO SELECTIVELY EXECUTE A COMMIT INSTRUCTION
    8.
    发明申请
    APPARATUSES AND METHODS TO SELECTIVELY EXECUTE A COMMIT INSTRUCTION 审中-公开
    选择和方法选择执行委托指令

    公开(公告)号：US20160283247A1

    公开(公告)日：2016-09-29

    申请号：US14668605

    申请日：2015-03-25

    Applicant: Intel Corporation

    Inventor： Girish Venkatasubramanian ,  Ethan Schuchman ,  David Keppel ,  Sebastian Winkel ,  David N. Mackintosh ,  Jaroslaw Topp

    IPC: G06F9/38

    CPC classification number: G06F9/30087 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/3859 ,  G06F9/3861 ,  G06F9/3863 ,  G06F9/455 ,  G06F9/45516 ,  G06F9/4552

    Abstract: Methods and apparatuses relating to selectively executing a commit instruction. In one embodiment, a data storage device stores code that when executed by a hardware processor causes the hardware processor to perform the following: translating an instruction into a translated instruction to be executed by the hardware processor, marking a commit instruction one of for execution and for optional execution by the hardware processor, and including a hint for a commit instruction marked for optional execution; and a hardware commit unit to determine if the commit instruction marked for optional execution is to be executed based on the hint.

    Abstract translation: 与选择性地执行提交指令有关的方法和装置。 在一个实施例中，数据存储装置存储当硬件处理器执行时硬件处理器执行以下操作的代码：将指令转换成由硬件处理器执行的转换指令，标记提交指令以执行和 用于硬件处理器的可选执行，并且包括用于可选执行标记的提交指令的提示; 以及硬件提交单元，用于基于提示来确定标记为可选执行的提交指令是否被执行。

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