公开(公告)号：US20180226887A1

公开(公告)日：2018-08-09

申请号：US15944214

申请日：2018-04-03

Applicant: Intel Corporation

Inventor： Jaydeep Kulkarni ,  Yong Shim ,  Pascal A. Meinerzhagen ,  Muhammad M. Khellah

IPC: H02M3/07 ,  H03K5/19 ,  H03K3/03

Abstract: Some embodiments include apparatus and methods using a charge pump coupled to a first supply power node and a second supply power node. The charge pump is arranged to transfer charge from the first supply power node to the second supply power node during a first time interval and to transfer charge from the second supply power node to the first supply power node during a second time interval.

公开(公告)号：US20240118826A1

公开(公告)日：2024-04-11

申请号：US17963313

申请日：2022-10-11

Applicant: Intel Corporation

Inventor： Amlan Ghosh ,  Feroze Merchant ,  Jaydeep Kulkarni ,  John R. Riley

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: A memory device includes at least one bitcell coupled to a local bitline. The at least one bitcell includes multiple sets of a plurality of transistor devices. The first set of the plurality of transistor devices is configured to form a single write (1W) port for receiving digital data. The second set of the plurality of transistor devices is configured as an inverter pair. The inverter pair stores the digital data. The third set of the plurality of transistor devices is configured to form a single read (1R) port. The 1R port can be used to access the digital data stored at the inverter pair and output the digital data on the local bitline. The plurality of transistor devices includes an equal number of P-channel transistor devices and N-channel transistor devices.

公开(公告)号：US10666259B1

公开(公告)日：2020-05-26

申请号：US16229617

申请日：2018-12-21

Applicant: Intel Corporation

Inventor： Andres Malavasi Mora ,  Jaydeep Kulkarni ,  Anupama Thaploo ,  Muhammad Khellah

IPC: H03K19/082 ,  H03K19/0175 ,  H03K19/0948

Abstract: Described is a level-shifter that can save area between voltage domains with limited voltage differential, and further save power by steering current between two power supply rails. The level-shifter comprises: an input to receive a first signal between a first reference rail and a second reference rail; an output to provide a second signal the first reference rail and a third reference rail, wherein in a voltage level of the third reference rail is higher than a voltage level of the second reference rail, and wherein a voltage level of the first reference is lower than the voltage level of the second reference rail and the third reference rail; and a circuitry coupled to the input and the output, wherein the circuitry is to steer current from the third reference rail to the second reference rail.

公开(公告)号：US10199091B2

公开(公告)日：2019-02-05

申请号：US15373048

申请日：2016-12-08

Applicant: Intel Corporation

Inventor： Minki Cho ,  Jaydeep Kulkarni ,  Carlos Tokunaga ,  Muhammad Khellah ,  James Tschanz

IPC: G11C5/14 ,  G11C11/417 ,  G11C11/413 ,  G11C29/24 ,  G11C29/04 ,  G11C29/12 ,  G11C29/52 ,  G11C11/412 ,  G11C29/50

Abstract: An apparatus is described. The apparatus includes a semiconductor chip. The semiconductor chip includes a memory having multiple storage cells. The storage cells are to receive a supply voltage. The semiconductor chip includes supply voltage retention circuitry. The supply voltage retention circuitry is to determine a level of the supply voltage at which the storage cells are able to retain their respective data. The supply voltage retention circuitry is to receive the supply voltage during a stress mode of the supply voltage retention circuitry. The supply voltage retention circuitry is to more weakly retain its stored information than the storage cells during a measurement mode at which the level is determined.

公开(公告)号：US10014767B2

公开(公告)日：2018-07-03

申请号：US15081445

申请日：2016-03-25

Applicant: Intel Corporation

Inventor： Jaydeep Kulkarni ,  Yong Shim ,  Pascal A. Meinerzhagen ,  Muhammad M. Khellah

IPC: G05F1/10 ,  H02M3/07 ,  H03K3/03 ,  H03K5/19

CPC classification number: H02M3/07 ,  H02M2001/0032 ,  H03K3/0315 ,  H03K5/19

Abstract: Some embodiments include apparatus and methods using a charge pump coupled to a first supply power node and a second supply power node. The charge pump is arranged to transfer charge from the first supply power node to the second supply power node during a first time interval and to transfer charge from the second supply power node to the first supply power node during a second time interval.

公开(公告)号：US20180130509A1

公开(公告)日：2018-05-10

申请号：US15863382

申请日：2018-01-05

Applicant: Intel Corporation

Inventor： Jaydeep Kulkarni

IPC: G11C7/12 ,  G11C8/08 ,  G11C8/10

CPC classification number: G11C7/12 ,  G11C7/1048 ,  G11C8/08 ,  G11C8/10 ,  G11C17/12 ,  G11C2207/005

Abstract: Some embodiments include apparatuses and methods having non-volatile memory cells, a data line associated with a group of non-volatile memory cells of the non-volatile memory cells, a first transistor coupled to the data line and a node, a second transistor coupled to the node and an additional node, a pull-up component coupled to the node and a supply node, and an additional pull-up component coupled to the additional node and the supply node.