公开(公告)号：US11908542B2

公开(公告)日：2024-02-20

申请号：US16725747

申请日：2019-12-23

Applicant: Intel Corporation

Inventor： Charles Augustine ,  Somnath Paul ,  Turbo Majumder ,  Iqbal Rajwani ,  Andrew Lines ,  Altug Koker ,  Lakshminarayanan Striramassarma ,  Muhammad Khellah

IPC: G11C7/10 ,  G11C7/12 ,  G11C7/22

CPC classification number: G11C7/1048 ,  G11C7/1006 ,  G11C7/12 ,  G11C7/22

Abstract: Prior knowledge of access pattern is leveraged to improve energy dissipation for general matrix operations. This improves memory access energy for a multitude of applications such as image processing, deep neural networks, and scientific computing workloads, for example. In some embodiments, prior knowledge of access pattern allows for burst read and/or write operations. As such, burst mode solution can provide energy savings in both READ (RD) and WRITE (WR) operations. For machine learning or inference, the weight values are known ahead in time (e.g., inference operation), and so the unused bytes in the cache line are exploited to store a sparsity map that is used for disabling read from either upper or lower half of the cache line, thus saving dynamic capacitance.

公开(公告)号：US10666259B1

公开(公告)日：2020-05-26

申请号：US16229617

申请日：2018-12-21

Applicant: Intel Corporation

Inventor： Andres Malavasi Mora ,  Jaydeep Kulkarni ,  Anupama Thaploo ,  Muhammad Khellah

IPC: H03K19/082 ,  H03K19/0175 ,  H03K19/0948

Abstract: Described is a level-shifter that can save area between voltage domains with limited voltage differential, and further save power by steering current between two power supply rails. The level-shifter comprises: an input to receive a first signal between a first reference rail and a second reference rail; an output to provide a second signal the first reference rail and a third reference rail, wherein in a voltage level of the third reference rail is higher than a voltage level of the second reference rail, and wherein a voltage level of the first reference is lower than the voltage level of the second reference rail and the third reference rail; and a circuitry coupled to the input and the output, wherein the circuitry is to steer current from the third reference rail to the second reference rail.

公开(公告)号：US10665222B2

公开(公告)日：2020-05-26

申请号：US16022376

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Suyoung Bang ,  Muhammad Khellah ,  Somnath Paul ,  Charles Augustine ,  Turbo Majumder ,  Wootaek Lim ,  Tobias Bocklet ,  David Pearce

IPC: G01L15/00 ,  G10L15/02 ,  G10L25/03 ,  G10L15/20 ,  G10L25/24 ,  G10L25/18 ,  G10L25/09

Abstract: A system, article, and method provide temporal-domain feature extraction for automatic speech recognition.

公开(公告)号：US10374584B1

公开(公告)日：2019-08-06

申请号：US15916130

申请日：2018-03-08

Applicant: Intel Corporation

Inventor： Charles Augustine ,  Muhammad Khellah ,  Arvind Raman ,  Feroze Merchant ,  Ashish Choubal

IPC: H03K3/037 ,  G01R31/3185

Abstract: An apparatus comprising: a flip-flip comprising a master stage and a slave stage, wherein the slave stage is coupled to the master stage, wherein the master and slave stages are coupled to a first power supply rail; and a scan circuitry coupled to the slave stage of the flip-flip, wherein at least a portion of the scan circuitry is coupled to a second power supply rail.

公开(公告)号：US20190115011A1

公开(公告)日：2019-04-18

申请号：US15786803

申请日：2017-10-18

Applicant: Intel Corporation

Inventor： Muhammad Khellah ,  Oren Arad ,  Binuraj Ravindran ,  Somnath Paul ,  Charles Augustine ,  Bruno Umbria Pedroni

IPC: G10L15/02 ,  G10L25/30 ,  G10L15/06 ,  G06N3/04

CPC classification number: G10L15/02 ,  G06N3/049 ,  G10L15/063 ,  G10L15/16 ,  G10L25/12 ,  G10L25/24 ,  G10L25/30 ,  G10L2015/0635 ,  G10L2015/088

Abstract: An example apparatus for detecting keywords in audio includes an audio receiver to receive audio comprising a keyword to be detected. The apparatus also includes a spike transducer to convert the audio into a plurality of spikes. The apparatus further includes a spiking neural network to receive one or more of the spikes and generate a spike corresponding to a detected keyword.

公开(公告)号：US10199091B2

公开(公告)日：2019-02-05

申请号：US15373048

申请日：2016-12-08

Applicant: Intel Corporation

Inventor： Minki Cho ,  Jaydeep Kulkarni ,  Carlos Tokunaga ,  Muhammad Khellah ,  James Tschanz

IPC: G11C5/14 ,  G11C11/417 ,  G11C11/413 ,  G11C29/24 ,  G11C29/04 ,  G11C29/12 ,  G11C29/52 ,  G11C11/412 ,  G11C29/50

Abstract: An apparatus is described. The apparatus includes a semiconductor chip. The semiconductor chip includes a memory having multiple storage cells. The storage cells are to receive a supply voltage. The semiconductor chip includes supply voltage retention circuitry. The supply voltage retention circuitry is to determine a level of the supply voltage at which the storage cells are able to retain their respective data. The supply voltage retention circuitry is to receive the supply voltage during a stress mode of the supply voltage retention circuitry. The supply voltage retention circuitry is to more weakly retain its stored information than the storage cells during a measurement mode at which the level is determined.

公开(公告)号：US12237832B2

公开(公告)日：2025-02-25

申请号：US17479963

申请日：2021-09-20

Applicant: Intel Corporation

Inventor： Miguel Bautista Gabriel ,  Sriram Vangal ,  Patrick Koeberl ,  Pratik Patel ,  Muhammad Khellah ,  James Tschanz ,  Carlos Tokunaga ,  Suyoung Bang

IPC: H03K19/177 ,  G01R31/28 ,  H03K19/0175 ,  H03K19/0185 ,  H03K19/17768 ,  H03K19/17784

Abstract: A detection circuit includes a tunable delay circuit that generates a delayed signal and that receives a supply voltage. The detection circuit includes a control circuit that adjusts a delay provided by the tunable delay circuit to the delayed signal. The detection circuit includes a time-to-digital converter circuit that converts the delay provided by the tunable delay circuit to the delayed signal to a digital code and adjusts the digital code based on changes in the supply voltage. The control circuit causes the tunable delay circuit to maintain the delay provided to the delayed signal constant in response to the digital code reaching an alignment value. The detection circuit may continuously monitor timing margin of a data signal relative to a clock signal and update the digital code in every clock cycle. The detection circuit may be a security sensor that detects changes in the supply voltage.

公开(公告)号：US11489526B2

公开(公告)日：2022-11-01

申请号：US16882407

申请日：2020-05-22

Applicant: Intel Corporation

Inventor： Andres Malavasi Mora ,  Jaydeep Kulkarni ,  Anupama Thaploo ,  Muhammad Khellah

IPC: H03K19/082 ,  H03K19/0175 ,  H03K19/0948

Abstract: Described is a level-shifter that can save area between voltage domains with limited voltage differential, and further save power by steering current between two power supply rails. The level-shifter comprises: an input to receive a first signal between a first reference rail and a second reference rail; an output to provide a second signal the first reference rail and a third reference rail, wherein in a voltage level of the third reference rail is higher than a voltage level of the second reference rail, and wherein a voltage level of the first reference is lower than the voltage level of the second reference rail and the third reference rail; and a circuitry coupled to the input and the output, wherein the circuitry is to steer current from the third reference rail to the second reference rail.

公开(公告)号：US11211935B2

公开(公告)日：2021-12-28

申请号：US17020667

申请日：2020-09-14

Applicant: Intel Corporation

Inventor： Suyoung Bang ,  Eric Samson ,  Wootaek Lim ,  Charles Augustine ,  Muhammad Khellah

IPC: H03L7/081 ,  G04F10/00 ,  H03L7/085

Abstract: An all-digital voltage monitor (ADVM) generates a multi-bit output code that changes in proportion to a voltage being monitored, by leveraging the voltage impact on a gate delay. ADVM utilizes a simple delay chain, which receives a clock-cycle-long pulse every clock cycle, such that the monitored supply voltage is sampled for one full cycle every cycle. The outputs of all delay cells of the delay chain collectively represents a current voltage state as a digital thermometer code. In AVDM, a voltage droop event thus results in a decrease in the output code from a nominal value, while an overshoot results in an increase in the output code.

公开(公告)号：US20210240142A1

公开(公告)日：2021-08-05

申请号：US17125768

申请日：2020-12-17

Applicant: Intel Corporation

Inventor： Suyoung Bang ,  Wootaek Lim ,  Eric Samson ,  Charles Augustine ,  Muhammad Khellah

IPC: G05B11/42 ,  G05F1/46

Abstract: A distributed and scalable all-digital LDO (D-DLDO) voltage regulator allowing rapid scaling across technology nodes. The distributed DLDO includes many tillable DLDO units regulating a single supply voltage with a shared power distribution network (PDN). The D-DLDO includes an all-digital proportional-integral-derivative (PID) controller that receives a first code indicative of a voltage behavior on a power supply rail. A droop detector is provided to compare the first code with a threshold to determine a droop event, wherein information about the droop event is provided to the PID controller, wherein the PID controller generates a second code according to the first code and the information about the droop event. The DLDO includes a plurality of power gates that receive the second code.