公开(公告)号：US12112204B2

公开(公告)日：2024-10-08

申请号：US17884244

申请日：2022-08-09

Applicant: Intel Corporation

Inventor： Pratik M. Marolia ,  Aaron J. Grier ,  Henry M. Mitchel ,  Joseph Grecco ,  Michael C. Adler ,  Utkarsh Y. Kakaiya ,  Joshua D. Fender ,  Sundar Nadathur ,  Nagabhushan Chitlur

IPC: G06F9/50 ,  G06F9/46 ,  G06F9/48

CPC classification number: G06F9/5027 ,  G06F9/468 ,  G06F9/4843 ,  G06F9/5044

Abstract: A system comprising an accelerator circuit comprising an accelerator function unit to implement a first function, and one or more device feature header (DFH) circuits to provide attributes associated with the accelerator function unit, and a processor to retrieve the attributes of the accelerator function unit by traversing a device feature list (DFL) referencing the one or more DFH circuits, execute, based on the attributes, an application encoding the first function to cause the accelerator function unit to perform the first function.

公开(公告)号：US20240168828A1

公开(公告)日：2024-05-23

申请号：US18058420

申请日：2022-11-23

Applicant: Intel Corporation

Inventor： Joseph Grecco ,  Mukesh Gangadhar Bhavani Venkatesan

IPC: G06F9/54

CPC classification number: G06F9/544

Abstract: Embodiments described herein are generally directed to improving performance of a transactional API protocol by adaptively optimizing function call performance at runtime. In an example, a command stream is monitored that includes function calls associated with the transactional API to be carried out by an executer on behalf of an application. An amount of data transmitted over an interconnect between the application and the executer is reduced by: (i) identifying a sequence of multiple of the function calls that represents a batch and satisfies a set of one or more criteria; (ii) creating a template of the batch having a symbolic name and including placeholders for a subset of variable arguments of the multiple of the function calls; and (ii) after observing a subsequent occurrence of the sequence within the command stream, transmitting via the interconnect the symbolic name and values for the subset of variable arguments.

公开(公告)号：US11531635B2

公开(公告)日：2022-12-20

申请号：US17088513

申请日：2020-11-03

Applicant: Intel Corporation

Inventor： Susanne M. Balle ,  Evan Custodio ,  Francesc Guim Bernat ,  Sujoy Sen ,  Slawomir Putyrski ,  Paul Dormitzer ,  Joseph Grecco

IPC: G06F13/40 ,  G06F13/36

Abstract: Technologies for providing I/O channel abstraction for accelerator device kernels include an accelerator device comprising circuitry to obtain availability data indicative of an availability of one or more accelerator device kernels in a system, including one or more physical communication paths to each accelerator device kernel. The circuitry is also configured to determine whether to establish a logical communication path between a kernel of the present accelerator device and another accelerator device kernel and establish, in response to a determination to establish the logical communication path as a function of the obtained availability data, the logical communication path between the kernel of the present accelerator device and the other accelerator device kernel.

公开(公告)号：US11416300B2

公开(公告)日：2022-08-16

申请号：US16619442

申请日：2017-06-29

Applicant: INTEL CORPORATION

Inventor： Pratik M. Marolia ,  Aaron J. Grier ,  Henry M. Mitchel ,  Joseph Grecco ,  Michael C. Adler ,  Utkarsh Y. Kakaiya ,  Joshua D. Fender ,  Sundar Nadathur ,  Nagabhushan Chitlur

IPC: G06F9/50 ,  G06F9/46 ,  G06F9/48

Abstract: A system comprising an accelerator circuit comprising an accelerator function unit to implement a first function, and one or more device feature header (DFH) circuits to provide attributes associated with the accelerator function unit, and a processor to retrieve the attributes of the accelerator function unit by traversing a device feature list (DFL) referencing the one or more DFH circuits, execute, based on the attributes, an application encoding the first function to cause the accelerator function unit to perform the first function.

公开(公告)号：US10853296B2

公开(公告)日：2020-12-01

申请号：US16236255

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Susanne M. Balle ,  Evan Custodio ,  Francesc Guim Bernat ,  Sujoy Sen ,  Slawomir Putyrski ,  Paul Dormitzer ,  Joseph Grecco

IPC: G06F13/40 ,  G06F13/36

Abstract: Technologies for providing I/O channel abstraction for accelerator device kernels include an accelerator device comprising circuitry to obtain availability data indicative of an availability of one or more accelerator device kernels in a system, including one or more physical communication paths to each accelerator device kernel. The circuitry is also configured to determine whether to establish a logical communication path between a kernel of the present accelerator device and another accelerator device kernel and establish, in response to a determination to establish the logical communication path as a function of the obtained availability data, the logical communication path between the kernel of the present accelerator device and the other accelerator device kernel.