公开(公告)号：US20210305154A1

公开(公告)日：2021-09-30

申请号：US16829336

申请日：2020-03-25

Applicant: Intel Corporation

Inventor： Ying Wang ,  Yikang Deng ,  Junnan Zhao ,  Andrew James Brown ,  Cheng Xu ,  Kaladhar Radhakrishnan

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L49/02

Abstract: Disclosed herein are magnetic structures in integrated circuit (IC) package supports, as well as related methods and devices. For example, in some embodiments, an IC package support may include a conductive line, a magnetic structure around the conductive line, and material stubs at side faces of the magnetic structure.

公开(公告)号：US10971492B2

公开(公告)日：2021-04-06

申请号：US16855376

申请日：2020-04-22

Applicant: Intel Corporation

Inventor： Cheng Xu ,  Rahul Jain ,  Seo Young Kim ,  Kyu Oh Lee ,  Ji Yong Park ,  Sai Vadlamani ,  Junnan Zhao

IPC: H01L27/07 ,  H01L23/64 ,  H01L23/522 ,  H01L23/00 ,  H01L49/02

Abstract: Disclosed embodiments include an embedded thin-film capacitor and a magnetic inductor that are assembled in two adjacent build-up layers of a semiconductor package substrate. The thin-film capacitor is seated on a surface of a first of the build-up layers and the magnetic inductor is partially disposed in a recess in the adjacent build up layer. The embedded thin-film capacitor and the integral magnetic inductor are configured within a die shadow that is on a die side of the semiconductor package substrate.

公开(公告)号：US20210020558A1

公开(公告)日：2021-01-21

申请号：US17064085

申请日：2020-10-06

Applicant: Intel Corporation

Inventor： Yikang Deng ,  Ying Wang ,  Cheng Xu ,  Chong Zhang ,  Junnan Zhao

IPC: H01L23/498 ,  H01L23/538

Abstract: An electronic device may include a substrate, and the substrate may include one or more layers. The one or more layers may include a first dielectric material and one or more electrical traces. A cavity may be defined in the substrate, and the cavity may be adapted to receive one or more electrical components. One or more lateral traces may extend through a wall of the cavity. The lateral traces may provide electrical communication pathways between the substrate and the electrical components.

公开(公告)号：US20190393217A1

公开(公告)日：2019-12-26

申请号：US16402588

申请日：2019-05-03

Applicant: Intel Corporation

Inventor： Cheng Xu ,  Rahul Jain ,  Seo Young Kim ,  Kyu Oh Lee ,  Ji Yong Park ,  Sai Vadlamani ,  Junnan Zhao

IPC: H01L27/07 ,  H01L49/02 ,  H01L23/64 ,  H01L23/522 ,  H01L23/00

Abstract: Disclosed embodiments include an embedded thin-film capacitor and a magnetic inductor that are assembled in two adjacent build-up layers of a semiconductor package substrate. The thin-film capacitor is seated on a surface of a first of the build-up layers and the magnetic inductor is partially disposed in a recess in the adjacent build up layer. The embedded thin-film capacitor and the integral magnetic inductor are configured within a die shadow that is on a die side of the semiconductor package substrate.

公开(公告)号：US20190385780A1

公开(公告)日：2019-12-19

申请号：US16012259

申请日：2018-06-19

Applicant: Intel Corporation

Inventor： Cheng Xu ,  Yikang Deng ,  Kyu Oh Lee ,  Ji Yong Park ,  Srinivas Pietambaram ,  Ying Wang ,  Chong Zhang ,  Rui Zhang ,  Junnan Zhao

IPC: H01F27/28 ,  H01F27/24 ,  H04B5/00 ,  H01L21/822 ,  H01L23/522 ,  H01L49/02 ,  H01F41/04

Abstract: Techniques are provided for an inductor at a first level interface between a first die and a second die. In an example, the inductor can include a winding and a core disposed inside the winding. The winding can include first conductive traces of a first die, second conductive traces of a second die, and a plurality of connectors configured to connect the first die with the second die. Each connector of the plurality of connecters can be located between a trace of the first conductive traces and a corresponding trace of the second conductive traces.

公开(公告)号：US20190304661A1

公开(公告)日：2019-10-03

申请号：US15938119

申请日：2018-03-28

Applicant: Intel Corporation

Inventor： Cheng Xu ,  Kyu-Oh Lee ,  Junnan Zhao ,  Rahul Jain ,  Ji Yong Park ,  Sai Vadlamani ,  Seo Young Kim

IPC: H01F27/28 ,  H01F27/24 ,  H01F27/02

Abstract: Embodiments include an inductor that comprises an inductor trace and a magnetic body surrounding the inductor trace. In an embodiment, the magnetic body comprises a first step surface and a second step surface. Additional embodiments include an inductor that includes a barrier layer. In an embodiment, an inductor trace is formed over a first surface of the barrier layer. Embodiments include a first magnetic body over the inductor trace and the first surface of the barrier layer, and a second magnetic body over a second surface of the barrier layer opposite the first surface. In an embodiment, a width of the second magnetic body is greater than a width of the first magnetic body.

公开(公告)号：US11901115B2

公开(公告)日：2024-02-13

申请号：US17873509

申请日：2022-07-26

Applicant: Intel Corporation

Inventor： Kyu-Oh Lee ,  Rahul Jain ,  Sai Vadlamani ,  Cheng Xu ,  Ji Yong Park ,  Junnan Zhao ,  Seo Young Kim

IPC: H01F27/32 ,  H01L23/498 ,  H01F41/04 ,  H01L21/48 ,  H01F27/28 ,  H01L21/683 ,  H01L23/00

CPC classification number: H01F27/327 ,  H01F27/2804 ,  H01F41/043 ,  H01L21/486 ,  H01L21/4857 ,  H01L21/4867 ,  H01L23/49822 ,  H01L23/49838 ,  H01F2027/2809 ,  H01L21/6835 ,  H01L24/16 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/16227 ,  H01L2224/16267 ,  H01L2924/19042 ,  H01L2924/19102

Abstract: Apparatuses, systems and methods associated with a substrate assembly with an encapsulated magnetic feature for an inductor are disclosed herein. In embodiments, a substrate assembly may include a base substrate, a magnetic feature encapsulated within the base substrate, and a coil, wherein a portion of the coil extends through the magnetic feature. Other embodiments may be described and/or claimed.

公开(公告)号：US11557489B2

公开(公告)日：2023-01-17

申请号：US16113109

申请日：2018-08-27

Applicant: Intel Corporation

Inventor： Rahul Jain ,  Sai Vadlamani ,  Junnan Zhao ,  Ji Yong Park ,  Kyu Oh Lee ,  Cheng Xu

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/495 ,  H01L23/31

Abstract: Disclosed herein are cavity structures in integrated circuit (IC) package supports, as well as related methods and apparatuses. For example, in some embodiments, an IC package support may include: a cavity in a dielectric material, wherein the cavity has a bottom and sidewalls; conductive contacts at the bottom of the cavity, wherein the conductive contacts include a first material; a first peripheral material outside the cavity, wherein the first peripheral material is at the sidewalls of the cavity and proximate to the bottom of the cavity, and the first peripheral material includes the first material; and a second peripheral material outside the cavity, wherein the second peripheral material is at the sidewalls of the cavity and on the first peripheral material, and the second peripheral material is different than the first peripheral material.

公开(公告)号：US11450471B2

公开(公告)日：2022-09-20

申请号：US15938119

申请日：2018-03-28

Applicant: Intel Corporation

Inventor： Cheng Xu ,  Kyu-Oh Lee ,  Junnan Zhao ,  Rahul Jain ,  Ji Yong Park ,  Sai Vadlamani ,  Seo Young Kim

IPC: H01F27/24 ,  H01F27/28 ,  H01F27/02

Abstract: Embodiments include an inductor that comprises an inductor trace and a magnetic body surrounding the inductor trace. In an embodiment, the magnetic body comprises a first step surface and a second step surface. Additional embodiments include an inductor that includes a barrier layer. In an embodiment, an inductor trace is formed over a first surface of the barrier layer. Embodiments include a first magnetic body over the inductor trace and the first surface of the barrier layer, and a second magnetic body over a second surface of the barrier layer opposite the first surface. In an embodiment, a width of the second magnetic body is greater than a width of the first magnetic body.

公开(公告)号：US11443892B2

公开(公告)日：2022-09-13

申请号：US16020035

申请日：2018-06-27

Applicant: Intel Corporation

Inventor： Kyu-Oh Lee ,  Rahul Jain ,  Sai Vadlamani ,  Cheng Xu ,  Ji Yong Park ,  Junnan Zhao ,  Seo Young Kim

IPC: H01L27/32 ,  H01F27/32 ,  H01L23/498 ,  H01F41/04 ,  H01L21/48 ,  H01F27/28 ,  H01L21/683 ,  H01L23/00

Abstract: Apparatuses, systems and methods associated with a substrate assembly with an encapsulated magnetic feature for an inductor are disclosed herein. In embodiments, a substrate assembly may include a base substrate, a magnetic feature encapsulated within the base substrate, and a coil, wherein a portion of the coil extends through the magnetic feature. Other embodiments may be described and/or claimed.