公开(公告)号：US20220200788A1

公开(公告)日：2022-06-23

申请号：US17561558

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Timothy Verrall ,  Thomas Willhalm ,  Francesc Guim Bernat ,  Karthik Kumar ,  Ned M. Smith ,  Rajesh Poornachandran ,  Kapil Sood ,  Tarun Viswanathan ,  John J. Browne ,  Patrick Kutch

IPC: H04L9/08

Abstract: Technologies for accelerated key caching in an edge hierarchy include multiple edge appliance devices organized in tiers. An edge appliance device receives a request for a key, such as a private key. The edge appliance device determines whether the key is included in a local key cache and, if not, requests the key from an edge appliance device included in an inner tier of the edge hierarchy. The edge appliance device may request the key from an edge appliance device included in a peer tier of the edge hierarchy. The edge appliance device may activate per-tenant accelerated logic to identify one or more keys in the key cache for eviction. The edge appliance device may activate per-tenant accelerated logic to identify one or more keys for pre-fetching. Those functions of the edge appliance device may be performed by an accelerator such as an FPGA. Other embodiments are described and claimed.

公开(公告)号：US20220166847A1

公开(公告)日：2022-05-26

申请号：US17542175

申请日：2021-12-03

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Thomas Willhalm ,  Petar Torre ,  Ned Smith ,  Brinda Ganesh ,  Evan Custodio ,  Suraj Prabhakaran

IPC: H04L67/60 ,  H04L12/66 ,  H04L47/70 ,  H04L67/2885 ,  H04L67/5681

Abstract: Technologies for fulfilling service requests in an edge architecture include an edge gateway device to receive a request from an edge device or an intermediate tier device of an edge network to perform a function of a service by an entity hosting the service. The edge gateway device is to identify one or more input data to fulfill the request by the service and request the one or more input data from an edge resource identified to provide the input data. The edge gateway device is to provide the input data to the entity associated with the request.

公开(公告)号：US20220166846A1

公开(公告)日：2022-05-26

申请号：US17390658

申请日：2021-07-30

Applicant: Intel Corporation

Inventor： Ramanathan Sethuraman ,  Timothy Verrall ,  Ned M. Smith ,  Thomas Willhalm ,  Brinda Ganesh ,  Francesc Guim Bernat ,  Karthik Kumar ,  Evan Custodio ,  Suraj Prabhakaran ,  Ignacio Astilleros Diez ,  Nilesh K. Jain ,  Ravi Iyer ,  Andrew J. Herdrich ,  Alexander Vul ,  Patrick G. Kutch ,  Kevin Bohan ,  Trevor Cooper

IPC: H04L67/303 ,  H04L9/40 ,  H04L9/08 ,  H04L67/12

Abstract: Technologies for managing telemetry and sensor data on an edge networking platform are disclosed. According to one embodiment disclosed herein, a device monitors telemetry data associated with multiple services provided in the edge networking platform. The device identifies, for each of the services and as a function of the associated telemetry data, one or more service telemetry patterns. The device generates a profile including the identified service telemetry patterns.

公开(公告)号：US20220109610A1

公开(公告)日：2022-04-07

申请号：US17555109

申请日：2021-12-17

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Marcos Carranza ,  Cesar Martinez-Spessot ,  Han Lee

IPC: H04L41/0896 ,  H04L41/5022 ,  H04L41/5006 ,  H04L41/12

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to orchestrate intermittent surplus power in Edge networks. An example apparatus includes power unit analysis circuitry to identify a power surplus, analysis circuitry to (a) apply an acceleration factor to a first trigger threshold of a local task, the acceleration factor to set a second trigger threshold, and (b) designate the local task for early execution when a current metric corresponding to the local task satisfies the second trigger threshold, and adaptive power managing circuitry to execute the local task in response to detecting the designation for early execution.

公开(公告)号：US20220100498A1

公开(公告)日：2022-03-31

申请号：US17546033

申请日：2021-12-08

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar

IPC: G06F8/71

Abstract: Implementation of object versioning and consistency at scale is described. An example of a computer-readable storage medium includes instructions to receive a storage request from an object management authority to store a version of a data object at a storage appliance; generate a hash value of the data object; store the data object in a scratchpad storage; transmit a verification request for the hash value of the data object to an object versioning authority; and, upon receiving affirmative verification for the hash value, move the data object from the scratchpad storage to a media storage and transmit an acknowledgement to the object management authority.

公开(公告)号：US11271994B2

公开(公告)日：2022-03-08

申请号：US16234718

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Ned Smith ,  Thomas Willhalm ,  Karthik Kumar ,  Timothy Verrall

IPC: H04L29/08 ,  H04L67/1008 ,  H04L67/1021 ,  H04L67/10 ,  H04L67/61 ,  H04L67/63 ,  H04L67/00 ,  H04L67/59

Abstract: Technologies for providing selective offload of execution of an application to the edge include a device that includes circuitry to determine whether a section of an application to be executed by the device is available to be offloaded. Additionally, the circuitry is to determine one or more characteristics of an edge resource available to execute the section. Further, the circuitry is to determine, as a function of the one or more characteristics and a target performance objective associated with the section, whether to offload the section to the edge resource and offload, in response to a determination to offload the section, the section to the edge resource.

公开(公告)号：US11240155B2

公开(公告)日：2022-02-01

申请号：US16369430

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Ned M. Smith ,  Monica Kenguva ,  Rashmin Patel

IPC: G06F15/16 ,  G06F9/54 ,  H04L29/06 ,  H04L12/803 ,  H04L12/851 ,  H04L12/26 ,  H04L12/927 ,  H04L12/813 ,  H04L29/08

Abstract: Technologies for load balancing on a network device in an edge network are disclosed. According to one embodiment, a network device receives, in the edge network, a request to access a function. The request includes one or more performance requirements. The network device identifies, as a function of an evaluation of the performance requirements and on monitored properties of each device associated with the network device, one or more of the devices to service the request. The network device selects one of the identified devices according to a load balancing policy and sends the request to the selected device.

公开(公告)号：US20220014588A1

公开(公告)日：2022-01-13

申请号：US17485040

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Thomas Willhalm

IPC: H04L29/08 ,  G06F12/0817 ,  G06F13/36 ,  G06F13/16

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed that reduce latency and bandwidth consumption when sharing memory across a distributed coherent Edge computing system. The distributed coherent Edge computing system disclosed herein configures a compute express link (CXL) endpoint to share data between memories across an Edge platform. The CXL endpoint configures coherent memory domain(s) of memory addresses, which are initialized from an Edge device connected to the Edge platform. The CXL endpoint also configures coherency rule(s) for the coherent memory domain(s). The CXL endpoint is implemented to snoop the Edge platform in response to read and write requests from the Edge device. The CXL endpoint selectively snoops memory addresses within the coherent memory domain(s) that are defined as coherent based on the coherency rule(s).

公开(公告)号：US20220004468A1

公开(公告)日：2022-01-06

申请号：US17479267

申请日：2021-09-20

Applicant: Intel Corporation

Inventor： Thomas Willhalm ,  Francesc Guim Bernat ,  Karthik Kumar ,  Rita Gupta ,  Mark Schmisseur ,  Dimitrios Ziakas

IPC: G06F11/20 ,  G06F11/14 ,  G06F9/50 ,  G06F9/445 ,  G06F12/14

Abstract: An embodiment of an electronic apparatus may comprise one or more substrates, and a controller coupled to the one or more substrates, the controller to allocate a first secure portion of a pooled memory to a first instantiation of an application on a first node, and circuitry coupled to the one or more substrates and the controller, the circuitry to provide a failover interface for a second instantiation of the application on a second node to access the first secure portion of the pooled memory in the event of a failure of the first node. Other embodiments are disclosed and claimed.

公开(公告)号：US11176091B2

公开(公告)日：2021-11-16

申请号：US15719639

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Mark A. Schmisseur ,  Thomas Willhalm ,  Francesc Guim Bernat ,  Karthik Kumar

IPC: G06F17/00 ,  G06F16/13 ,  G06F16/22 ,  G06F16/178 ,  G06F16/25

Abstract: Techniques and apparatus for providing access to data in a plurality of storage formats are described. In one embodiment, for example, an apparatus may include logic, at least a portion of comprised in hardware coupled to the at least one memory, to determine a first storage format of a database operation on a database having a second storage format, and perform a format conversion process responsive to the first storage format being different than the second storage format, the format conversion process to translate a virtual address of the database operation to a physical address, and determine a converted physical address comprising a memory address according to the first storage format. Other embodiments are described and claimed.