公开(公告)号：US20200312665A1

公开(公告)日：2020-10-01

申请号：US16363688

申请日：2019-03-25

Applicant: Intel Corporation

Inventor： Suddhasattwa NAD ,  Jeremy ECTON ,  Bai NIE ,  Rahul MANEPALLI ,  Marcel WALL

IPC: H01L21/28 ,  H01L21/48 ,  H01L23/00

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, an electronic package comprises a package substrate, a first die over the package substrate, the first die having a first bump pitch, a second die over the package substrate, the second die having a second bump pitch that is greater than the first bump pitch, and a plurality of conductive traces over the package substrate, the plurality of conductive traces electrically coupling the first die to the second die. In an embodiment, a first end region of the plurality of conductive traces proximate to the first die has a first line space (L/S) dimension, and a second end region of the plurality of conductive traces proximate to the second die has a second L/S dimension. In an embodiment, the second L/S dimension is greater than the first L/S dimension.

公开(公告)号：US20200251332A1

公开(公告)日：2020-08-06

申请号：US16269357

申请日：2019-02-06

Applicant: Intel Corporation

Inventor： Suddhasattwa NAD ,  Roy DITTLER ,  Darko GRUJICIC ,  Marcel WALL ,  Rahul MANEPALLI

IPC: H01L21/02 ,  H01L21/768 ,  H01L21/285

Abstract: Embodiments include package substrates and a method of forming the package substrates. A package substrate includes a self-assembled monolayer (SAM) layer over a first dielectric, where the SAM layer includes first end groups and second end groups. The second end groups may include a plurality of hydrophobic moieties. The package substrate also includes a conductive pad on the first dielectric, where the conductive pad has a bottom surface, a top surface, and a sidewall, and where the SAM layer surrounds and contacts a surface of the sidewall of the conductive pad. The hydrophobic moieties may include fluorinated moieties. The conductive pad includes a copper material, where the top surface of the conductive pad has a surface roughness that is approximately equal to a surface roughness of the as-plated copper material. The SAM layer may have a thickness that is approximately 0.1 nm to 20 nm.

公开(公告)号：US20240213301A1

公开(公告)日：2024-06-27

申请号：US18089471

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Darko GRUJICIC ,  Thomas L. SOUNART ,  Benjamin DUONG ,  Kristof DARMAWIKARTA ,  Shayan KAVIANI ,  Suddhasattwa NAD ,  Mahdi MOHAMMADIGHALENI ,  Marcel WALL ,  Rengarajan SHANMUGAM

IPC: H01G4/33

CPC classification number: H01L28/40 ,  H01G4/33

Abstract: Embodiments disclosed herein include a package core. In an embodiment, the package core comprises a core substrate that includes glass. In an embodiment, a cavity is provided into the core substrate. In an embodiment, a capacitor is lining sidewalls of the cavity, and the capacitor comprises a first layer, a dielectric layer over the first layer, and a second layer over the dielectric layer.

公开(公告)号：US20240213132A1

公开(公告)日：2024-06-27

申请号：US18089476

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Kristof DARMAWIKARTA ,  Benjamin DUONG ,  Darko GRUJICIC ,  Shayan KAVIANI ,  Mahdi MOHAMMADIGHALENI ,  Suddhasattwa NAD ,  Thomas L. SOUNART ,  Marcel WALL ,  Ravindranath V. MAHAJAN ,  Rahul N. MANEPALLI

IPC: H01L23/498 ,  H01L27/01

CPC classification number: H01L23/49838 ,  H01L27/016 ,  H01L28/86 ,  H01L28/90 ,  H01L23/49822 ,  H01L23/49894 ,  H01L24/16

Abstract: Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a package substrate, where the package substrate comprises a plurality of stacked dielectric layers. In an embodiment, the electronic package further comprises an opening into the package substrate, where the opening passes through at least two of the plurality of dielectric layers. In an embodiment, a first pad is at the bottom of the opening, a capacitor is disposed in the opening, and a second pad is over the capacitor.

公开(公告)号：US20240006297A1

公开(公告)日：2024-01-04

申请号：US17853582

申请日：2022-06-29

Applicant: Intel Corporation

Inventor： Suddhasattwa NAD ,  Kristof DARMAWIKARTA ,  Srinivas V. PIETAMBARAM ,  Tarek A. IBRAHIM ,  Rahul N. MANEPALLI ,  Darko GRUJICIC ,  Marcel WALL ,  Yi YANG

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/538

CPC classification number: H01L23/49894 ,  H01L21/4846 ,  H01L23/538 ,  H01L21/481

Abstract: Embodiments herein relate to systems, apparatuses, or processes for forming a silicide and a silicon nitrate layer between a copper feature and dielectric to reduce delamination of the dielectric. Embodiments allow an unroughened surface for the copper feature to reduce the insertion loss for transmission lines that go through the unroughened surface of the copper. Embodiments may include sequential interlayers between a dielectric and copper. Other embodiments may be described and/or claimed.

公开(公告)号：US20240006283A1

公开(公告)日：2024-01-04

申请号：US17853487

申请日：2022-06-29

Applicant: Intel Corporation

Inventor： Suddhasattawa NAD ,  Rahul N. MANEPALLI ,  Gang DUAN ,  Srinivas V. PIETAMBARAM ,  Yi YANG ,  Marcel WALL ,  Darko GRUJICIC ,  Haobo CHEN ,  Aaron GARELICK

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49822 ,  H01L23/49866 ,  H01L21/4857 ,  H01L2224/16225 ,  H01L24/16

Abstract: Embodiments disclosed herein include package substrates and methods of forming such substrates. In an embodiment, a package substrate comprises a core, a first layer over the core, where the first layer comprises a metal, and a second layer over the first layer, where the second layer comprises an electrical insulator. In an embodiment, the package substrate further comprises a third layer over the second layer, where the third layer comprises a dielectric material, and where an edge of the core extends past edges of the first layer, the second layer, and the third layer.

公开(公告)号：US20230317584A1

公开(公告)日：2023-10-05

申请号：US17707371

申请日：2022-03-29

Applicant: Intel Corporation

Inventor： Yi YANG ,  Suddhasattwa NAD ,  Marcel WALL ,  Rahul N. MANEPALLI ,  Benjamin DUONG

IPC: H01L23/498 ,  H01L21/48 ,  H05K1/18

CPC classification number: H01L23/49822 ,  H01L23/49866 ,  H01L23/49894 ,  H01L21/4857 ,  H01L21/486 ,  H05K1/181 ,  H01L24/16

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a package substrate with a plurality of first layers, where the first layers comprise an organic material. In an embodiment, a trace is embedded in the package substrate. In an embodiment, a second layer is over the trace, where the second layer comprises silicon and nitrogen, and wherein the second layer is chemically bonded to one of the first layers by an oxygen containing ligand and/or a nitrogen containing ligand.

公开(公告)号：US20230317583A1

公开(公告)日：2023-10-05

申请号：US17707358

申请日：2022-03-29

Applicant: Intel Corporation

Inventor： Rahul N. MANEPALLI ,  Yi YANG ,  Suddhasattwa NAD ,  Benjamin DUONG ,  Marcel WALL

IPC: H01L23/498 ,  H01L21/48 ,  H05K1/18

CPC classification number: H01L23/49822 ,  H01L23/49866 ,  H01L23/49894 ,  H01L21/4857 ,  H05K1/181 ,  H01L24/16

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate with a plurality of first layers, where the first layers comprise an organic material. In an embodiment, a trace is embedded in the package substrate. In an embodiment, a second layer is over the trace, where the second layer comprises silicon, nitrogen, and a catalyst, and where the second layer is chemically bonded to one of the first layers.

公开(公告)号：US20190393183A1

公开(公告)日：2019-12-26

申请号：US16017393

申请日：2018-06-25

Applicant: Intel Corporation

Inventor： Suddhasattwa NAD ,  Rahul MANEPALLI ,  Marcel WALL

IPC: H01L23/00 ,  H01L23/29 ,  H01L21/48 ,  H01L21/56

Abstract: Embodiments include a package substrate, a method of forming the package substrate, and a self-assembled monolayers (SAM) layer. The package substrate includes a SAM layer on portions of a conductive pad, where the SAM layer includes alight-reflective moieties. The package substrate also includes a via on a surface portion of the conductive pad, and a dielectric on and around the via, the SAM layer, and the conductive pad, where the SAM layer surrounds and contacts a surface of the via. The SAM layer may be an interfacial organic layer. The light-reflective moieties may include a hemicyanine, a cyclic-hemicyanine, an oligothiophene, and/or a conjugated aromatic compound. The SAM layer may include a molecular structure having a first end group of a first monolayer, an intermediate group, a fifth end group of a second monolayer, and one or more of a first and second light-reflective moieties.