公开(公告)号：US20240222137A1

公开(公告)日：2024-07-04

申请号：US18091022

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Shaojiang CHEN ,  Jeremy D. ECTON ,  Oladeji FADAYOMI ,  Srinivas V. PIETAMBARAM ,  Matthew L. TINGEY

IPC: H01L21/3213 ,  H01L21/768 ,  H01L23/15 ,  H01L23/498

CPC classification number: H01L21/3213 ,  H01L21/76808 ,  H01L23/15 ,  H01L23/49827 ,  H01L23/5386

Abstract: Embodiments disclosed herein include electronic packages and methods of forming electronic packages. In an embodiment, the electronic package comprises a core, where the core comprises glass. In an embodiment, a through glass via (TGV) is provided through a thickness of the core, where a top surface of the TGV is not coplanar with a top surface of the core. In an embodiment, the electronic package further comprises a ridge on the top surface of the TGV, where the ridge is symmetric about a centerline of the TGV.

公开(公告)号：US20240203664A1

公开(公告)日：2024-06-20

申请号：US18081362

申请日：2022-12-14

Applicant: Intel Corporation

Inventor： Yosef KORNBLUTH ,  Bainye Francoise ANGOUA ,  Whitney BRYKS ,  Daniel ROSALES-YEOMANS ,  Aaditya Anand CANDADAI ,  Holly CLINGAN ,  Jade Sharee LEWIS ,  Patrick QUACH ,  Srinivas V. PIETAMBARAM

IPC: H01G4/33 ,  H01G4/10

CPC classification number: H01G4/33 ,  H01G4/105

Abstract: Embodiments disclosed herein include a core for a package substrate. In an embodiment, the core comprises a first substrate with a first surface and a second surface, a first recess into the first surface of the first substrate, a first layer in the first recess, where the first layer is electrically conductive, a second layer over the first layer, where the second layer is a dielectric layer, and a third layer over the second layer, where the third layer is electrically conductive. In an embodiment, the core further comprises a second substrate with a third surface and a fourth surface, where the third surface of the second substrate faces the first surface of the first substrate, a second recess in the third surface of the second substrate, and a fourth layer in the second recess, where the fourth layer is electrically conductive, and the fourth layer contacts the third layer.

公开(公告)号：US20240105575A1

公开(公告)日：2024-03-28

申请号：US17953206

申请日：2022-09-26

Applicant: Intel Corporation

Inventor： Jason M. GAMBA ,  Haifa HARIRI ,  Kristof DARMAWIKARTA ,  Srinivas V. PIETAMBARAM ,  Hiroki TANAKA ,  Kyle MCELHINNY ,  Xiaoying GUO ,  Steve S. CHO ,  Ali LEHAF ,  Haobo CHEN ,  Bai NIE ,  Numair AHMED

IPC: H01L23/498 ,  C25D3/12 ,  C25D3/48 ,  C25D3/50 ,  C25D7/12 ,  H01L21/48

CPC classification number: H01L23/49838 ,  C25D3/12 ,  C25D3/48 ,  C25D3/50 ,  C25D7/123 ,  H01L21/481 ,  H01L21/4846 ,  H01L23/49866 ,  H01L24/16

Abstract: Embodiments disclosed herein include package substrates and methods of forming package substrates. In an embodiment, the package substrate comprises a core, and a pad over the core, where the pad has a first width. In an embodiment, a surface finish is over the pad, where the surface finish has a second width that is substantially equal to the first width. In an embodiment, the package substrate further comprises a solder resist over the pad, where the solder resist comprises an opening that exposes a portion of the surface finish. In an embodiment, the opening has a third width that is smaller than the second width.

公开(公告)号：US20240071883A1

公开(公告)日：2024-02-29

申请号：US17893893

申请日：2022-08-23

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Sashi S. KANDANUR ,  Suddhasattwa NAD ,  Srinivas V. PIETAMBARAM ,  Gang DUAN ,  Jeremy D. ECTON

IPC: H01L23/498 ,  H01L23/15 ,  H01L23/544

CPC classification number: H01L23/49827 ,  H01L23/15 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/544 ,  H01L24/16 ,  H01L2224/16225

Abstract: Embodiments disclosed herein include cores for package substrates. In an embodiment, the core comprises a first substrate, where the first substrate comprises glass. In an embodiment, the core further comprises a first through glass via (TGV) through the first substrate and a second substrate, where the second substrate comprises glass. In an embodiment, the core further comprises a second TGV through the second substrate, where the first TGV is aligned with the second TGV.

公开(公告)号：US20240055345A1

公开(公告)日：2024-02-15

申请号：US17886278

申请日：2022-08-11

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Srinivas V. PIETAMBARAM ,  Gang DUAN ,  Suddhasattwa NAD ,  Jeremy D. ECTON ,  Rahul N. MANEPALLI

IPC: H01L23/522 ,  H01L49/02 ,  H01G11/70 ,  H01L23/15

CPC classification number: H01L23/5223 ,  H01L28/40 ,  H01G11/70 ,  H01L23/15

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a substrate, where the substrate comprises glass. In an embodiment, a pillar is over the substrate, and a capacitor is over the pillar. In an embodiment, the capacitor comprises a first conductive layer on the pillar, a dielectric layer over the first conductive layer, and a second conductive layer over the dielectric layer.

公开(公告)号：US20230420348A1

公开(公告)日：2023-12-28

申请号：US17852039

申请日：2022-06-28

Applicant: Intel Corporation

Inventor： Jieying KONG ,  Whitney BRYKS ,  Dilan SENEVIRATNE ,  Suddhasattwa NAD ,  Srinivas V. PIETAMBARAM

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49822 ,  H01L23/49894 ,  H01L21/4857 ,  H01L2224/16225 ,  H01L24/16

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first layer, where the first layer is a dielectric material, and a trace on the first layer. In an embodiment, a pad is on the first layer, and a liner is over the first layer, the trace, and the pad, where a hole is provided through the liner. In an embodiment, the electronic package further comprises a second layer over the first layer, the trace, the pad, and the liner.

公开(公告)号：US20230099632A1

公开(公告)日：2023-03-30

申请号：US17485248

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Andrew COLLINS ,  Srinivas V. PIETAMBARAM ,  Tarek A. IBRAHIM ,  Aleksandar ALEKSOV ,  Telesphor KAMGAING

IPC: H01L23/498 ,  H01L23/15 ,  H01L27/02

Abstract: Embodiments disclosed herein include disaggregated die modules. In an embodiment, a disaggregated die module comprises a plurality of core logic blocks. In an embodiment, the disaggregated die module further comprises a first IO interface, where the first IO interface is adjacent to an edge of the disaggregated die module, and a second IO interface, where the second IO interface is set away from the edge of the disaggregated die module.

公开(公告)号：US20230093258A1

公开(公告)日：2023-03-23

申请号：US17482830

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Jeremy D. ECTON ,  Srinivas V. PIETAMBARAM ,  Brandon C. MARIN ,  Haobo CHEN ,  Leonel ARANA

IPC: H01L23/498 ,  H01L23/15 ,  H01L21/48

Abstract: Embodiments include electronic packages and methods of forming such packages. In an embodiment, an electronic package comprises a first substrate, and a second substrate coupled to the first substrate. In an embodiment, the second substrate comprises a core, and the core comprises an organic material. In an embodiment, a third substrate is coupled to the second substrate, and the third substrate comprises a glass layer.

公开(公告)号：US20230092740A1

公开(公告)日：2023-03-23

申请号：US17481257

申请日：2021-09-21

Applicant: Intel Corporation

Inventor： Srinivas V. PIETAMBARAM ,  Rahul N. MANEPALLI ,  Ravindra TANIKELLA

IPC: H01L23/498 ,  H01L25/065 ,  H01L23/538 ,  H01L21/48 ,  H01L23/00

Abstract: Embodiments disclosed herein include electronic packages and methods of assembling such electronic packages. In an embodiment, an electronic package comprises a core, where the core comprises glass. In an embodiment, a hole is through a thickness of the core, and a plug fills the hole, where the plug comprises a polymeric material. In an embodiment, first layers are over the core, where the first layers comprise a dielectric material; and second layers are under the core, where the second layers comprise the dielectric material.

公开(公告)号：US20220199515A1

公开(公告)日：2022-06-23

申请号：US17690964

申请日：2022-03-09

Applicant: Intel Corporation

Inventor： Srinivas V. PIETAMBARAM ,  Jung Kyu HAN ,  Ali LEHAF ,  Steve CHO ,  Thomas HEATON ,  Hiroki TANAKA ,  Kristof DARMAWIKARTA ,  Robert Alan MAY ,  Sri Ranga Sai BOYAPATI

IPC: H01L23/498 ,  H01L23/538 ,  H01L25/18 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00

Abstract: A package assembly includes a substrate and at least a first die having a first contact array and a second contact array. First and second via assemblies are respectively coupled with the first and second contact arrays. Each of the first and second via assemblies includes a base pad, a cap assembly, and a via therebetween. One or more of the cap assembly or the via includes an electromigration resistant material to isolate each of the base pad and the cap assembly. Each first cap assembly and via of the first via assemblies has a first assembly profile less than a second assembly profile of each second cap assembly and via of the second via assemblies. The first and second cap assemblies have a common applied thickness in an application configuration. The first and second cap assemblies have a thickness variation of ten microns or less in a reflowed configuration.