公开(公告)号：US10757487B2

公开(公告)日：2020-08-25

申请号：US15396151

申请日：2016-12-30

Applicant: INTEL CORPORATION

Inventor： Mohan J. Kumar ,  Murugasamy K. Nachimuthu ,  Aaron Gorius ,  Michael Crocker

IPC: G06F9/46 ,  H04Q11/00 ,  G06F1/20 ,  G06F16/901 ,  G02B6/38 ,  G02B6/42 ,  G02B6/44 ,  G06F1/18 ,  G06F3/06 ,  G06F8/65 ,  G06F9/30 ,  G06F9/38 ,  G06F9/4401 ,  G06F9/50 ,  G06F9/54 ,  G06F12/109 ,  G06F12/14 ,  G06F13/16 ,  G06F13/40 ,  G08C17/02 ,  G11C5/02 ,  G11C7/10 ,  G11C11/56 ,  G11C14/00 ,  H03M7/30 ,  H03M7/40 ,  H04B10/25 ,  H04L12/24 ,  H04L12/26 ,  H04L12/851 ,  H04L12/811 ,  H04L12/931 ,  H04L29/08 ,  H04L29/06 ,  H05K5/02 ,  H05K7/14 ,  H04L12/911 ,  B25J15/00 ,  B65G1/04 ,  H05K7/20 ,  H04L12/939 ,  H04W4/02 ,  H04L12/751 ,  G06F13/42 ,  H05K1/18 ,  G05D23/19 ,  G05D23/20 ,  H04L12/927 ,  H05K1/02 ,  H04L12/781 ,  H04Q1/04 ,  G06F12/0893 ,  H05K13/04 ,  G11C5/06 ,  G06F11/14 ,  G06F11/34 ,  G06F12/0862 ,  G06F15/80 ,  H04L12/919 ,  G06F12/10 ,  G06Q10/06 ,  G07C5/00 ,  H04L12/28 ,  H04L29/12 ,  H04L9/06 ,  H04L9/14 ,  H04L9/32 ,  H04L12/933 ,  H04L12/947 ,  H04W4/80 ,  G06Q10/08 ,  G06Q10/00 ,  G06Q50/04

Abstract: Examples may include techniques to allocate physical accelerator resources from pools of accelerator resources. In particular, virtual computing devices can be composed from physical resources and physical accelerator resources dynamically allocated to the virtual computing devices. The present disclosure provides that physical accelerator resources can be dynamically allocated, or composed, to a virtual computing device despite not being physically coupled to other components in the virtual device.

公开(公告)号：US10719443B2

公开(公告)日：2020-07-21

申请号：US16363992

申请日：2019-03-25

Applicant: Intel Corporation

Inventor： Raj K. Ramanujan ,  Rajat Agarwal ,  Kai Cheng ,  Taarinya Polepeddi ,  Camille C. Raad ,  David J. Zimmerman ,  Muthukumar P. Swaminathan ,  Dimitrios Ziakas ,  Mohan J. Kumar ,  Bassam N. Coury ,  Glenn J. Hinton

IPC: G11C11/406 ,  G06F12/0811 ,  G06F12/0895 ,  G06F12/0897 ,  G11C14/00

Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.”

公开(公告)号：US10687434B2

公开(公告)日：2020-06-16

申请号：US15395855

申请日：2016-12-30

Applicant: INTEL CORPORATION

Inventor： Mohan J. Kumar ,  Murugasamy K. Nachimuthu

IPC: G06F15/177 ,  H05K7/14 ,  G06F3/06

Abstract: Mechanisms for SAS-free cabling in Rack Scale Design (RSD) environments and associated methods, apparatus, and systems. Pooled compute drawers containing multiple compute nodes are coupled to pooled storage drawers using fabric infrastructure, such as Ethernet links and switches. The pooled storage drawers includes a storage distributor that is coupled to a plurality of storage devices and includes one or more fabric ports and a PCIe switch with multiple PCIe ports. Under one configuration, the PCIe ports are connected to one or more IO hubs including a PCIe switch coupled to multiple storage device interfaces that are coupled to the storage devices. In another configuration, the PCIe ports are connected directly to PCIe storage devices. The storage distributor implements a NVMe-oF server driver that interacts with an NVMe-oF client driver running on compute nodes or a fabric switch. The drivers logically couple the storage devices over the fabric infrastructure to the compute nodes in a manner that appears the storage devices are local devices.

公开(公告)号：US20190251264A1

公开(公告)日：2019-08-15

申请号：US16392863

申请日：2019-04-24

Applicant: Intel Corporation

Inventor： Sarathy Jayakumar ,  Mohan J. Kumar ,  Ron Story ,  Mahesh Natu

IPC: G06F21/57 ,  G06F9/455 ,  G06F9/4401 ,  G06F9/448

CPC classification number: G06F21/572 ,  G06F9/4411 ,  G06F9/449 ,  G06F9/45558 ,  G06F2009/45579 ,  G06F2009/45583

Abstract: Technologies for secure native code invocation include a computing device having an operating system and a firmware environment. The operating system executes a firmware method in an operating system context using a virtual machine. In response to invoking the firmware method, the operating system invokes a callback to a bridge driver in the operating system context. In response to the callback, the bridge driver invokes a firmware runtime service in the operating system context. The firmware environment executes a native code handler in the operating system context in response to invoking the firmware runtime service. The native code handler may be executed in a de-privileged container. The firmware method may process results data stored in a firmware mailbox by the native code handler, which may include accessing a hardware resource using a firmware operation region. Other embodiments are described and claimed.

公开(公告)号：US10324852B2

公开(公告)日：2019-06-18

申请号：US15374796

申请日：2016-12-09

Applicant: INTEL CORPORATION

Inventor： Theodros Yigzaw ,  Ashok Raj ,  Robert C. Swanson ,  Mohan J. Kumar

IPC: G06F11/00 ,  G06F12/0868 ,  G06F11/20 ,  G06F12/109

Abstract: One embodiment provides for a data processing system comprising a multi-level system memory including a first memory level of volatile memory and a second memory level that is larger and slower in comparison with the first memory level. The second memory level includes non-volatile memory and can additionally include volatile memory. The multi-level system memory includes a multi-level memory controller including logic to manage a list of faulty addresses within the multi-level system memory. The multi-level memory controller can manage a list of faulty addresses. The multi-level memory controller is configured to satisfy a request for data stored in the first memory level from the second memory level when the data is stored in an address on the list of faulty addresses.

公开(公告)号：US20180324052A1

公开(公告)日：2018-11-08

申请号：US15585936

申请日：2017-05-03

Applicant: Intel Corporation

Inventor： Murugasamy K. Nachimuthu ,  Mohan J. Kumar

IPC: H04L12/24

CPC classification number: H04L41/14 ,  H04L41/5009 ,  H04L67/10

Abstract: Trusted platform telemetry mechanisms and associated methods, apparatus, and firmware components. Trusted telemetry mechanisms are provided for securely collecting platform telemetry data from telemetry data sources on a compute platform, such as machine specific registers (MSRs), device registers, system management bus (SMBus) and memory controllers. The telemetry data is collected from the telemetry data sources using various mechanisms, and securely stored on the compute platform in a manner that is inaccessible to software running on the compute platform. A submission queue and completion queue model may also be implemented to facilitate collection of telemetry data. In addition, a memory-mapped input-output (MMIO) aliasing scheme is provided to facilitate collection of telemetry data from platform telemetry data sources using various access mechanisms.

公开(公告)号：US20180287949A1

公开(公告)日：2018-10-04

申请号：US15472910

申请日：2017-03-29

Applicant: Intel Corporation

Inventor： Mohan J. Kumar ,  Murugasamy K. Nachimuthu ,  Vasudevan Srinivasan

IPC: H04L12/851 ,  H04L12/927 ,  H04L12/24 ,  H04L29/08 ,  G06F9/50

Abstract: A rack system including a plurality of nodes can implement thermal/power throttling, sub-node composition, and processing balancing based on voltage/frequency. In the thermal/power throttling, at least one resource is throttled, based at least in part on a heat event or a power event. In the sub-node composition, a plurality of computing cores is divided into a target number of domains. In the processing balancing based on voltage/frequency, a first core performs a first processing job at a first voltage or frequency, and a second core performs a second processing job at a second voltage or frequency different from the first voltage or frequency.

公开(公告)号：US20180219797A1

公开(公告)日：2018-08-02

申请号：US15620376

申请日：2017-06-12

Applicant: Intel Corporation

Inventor： Sujoy Sen ,  Mohan J. Kumar ,  Donald L. Faw ,  Susanne M. Balle ,  Narayan Ranganathan

IPC: H04L12/927 ,  H04L29/08 ,  H04L12/865

CPC classification number: H04L47/803 ,  H04L47/6275 ,  H04L49/109 ,  H04L67/1097 ,  H04L67/34

Abstract: Technologies for pooling accelerators over fabric are disclosed. In the illustrative embodiment, an application may access an accelerator device over an application programming interface (API) and the API can access an accelerator device that is either local or a remote accelerator device that is located on a remote accelerator sled over a network fabric. The API may employ a send queue and a receive queue to send and receive command capsules to and from the accelerator sled.

公开(公告)号：US20180188966A1

公开(公告)日：2018-07-05

申请号：US15393935

申请日：2016-12-29

Applicant: Intel Corporation

Inventor： Sarathy Jayakumar ,  Mohan J. Kumar ,  Ashok Raj ,  Hemalatha Gurumoorthy ,  Ronald N. Story

IPC: G06F3/06

CPC classification number: G06F3/065 ,  G06F3/0619 ,  G06F3/0673 ,  G06F11/1666 ,  G06F11/2056 ,  G06F11/2094

Abstract: A systems and methods for dynamic address based minoring are disclosed. A system may include a processor, comprising a mirror address range register to store data indicating a location and a size of a first portion of a system memory to be mirrored. The processor may further include a memory controller coupled to the mirror address range register and including circuitry to cause a second portion of the system memory to mirror the first portion of the system memory.

公开(公告)号：US20180165207A1

公开(公告)日：2018-06-14

申请号：US15374796

申请日：2016-12-09

Applicant: INTEL CORPORATION

Inventor： Theodros Yigzaw ,  Ashok Raj ,  Robert C. Swanson ,  Mohan J. Kumar

IPC: G06F12/0868 ,  G06F11/20 ,  G06F12/109

CPC classification number: G06F12/0868 ,  G06F11/2094 ,  G06F12/0804 ,  G06F12/0866 ,  G06F12/109 ,  G06F2201/805 ,  G06F2201/82 ,  G06F2212/1032 ,  G06F2212/202 ,  G06F2212/2022 ,  G06F2212/222

Abstract: One embodiment provides for a data processing system comprising a multi-level system memory including a first memory level of volatile memory and a second memory level that is larger and slower in comparison with the first memory level. The second memory level includes non-volatile memory and can additionally include volatile memory. The multi-level system memory includes a multi-level memory controller including logic to manage a list of faulty addresses within the multi-level system memory. The multi-level memory controller can manage a list of faulty addresses. The multi-level memory controller is configured to satisfy a request for data stored in the first memory level from the second memory level when the data is stored in an address on the list of faulty addresses.