公开(公告)号：US10784874B1

公开(公告)日：2020-09-22

申请号：US16783096

申请日：2020-02-05

Applicant: Intel Corporation

Inventor： Suyoung Bang ,  Eric Samson ,  Wootaek Lim ,  Charles Augustine ,  Muhammad Khellah

IPC: H03L7/02 ,  H03M1/30 ,  H03M1/38 ,  G04F10/00 ,  H03L7/081 ,  H03L7/085

Abstract: An all-digital voltage monitor (ADVM) generates a multi-bit output code that changes in proportion to a voltage being monitored, by leveraging the voltage impact on a gate delay. ADVM utilizes a simple delay chain, which receives a clock-cycle-long pulse every clock cycle, such that the monitored supply voltage is sampled for one full cycle every cycle. The outputs of all delay cells of the delay chain collectively represents a current voltage state as a digital thermometer code. In AVDM, a voltage droop event thus results in a decrease in the output code from a nominal value, while an overshoot results in an increase in the output code.

公开(公告)号：US20190288681A1

公开(公告)日：2019-09-19

申请号：US15925396

申请日：2018-03-19

Applicant: Intel Corporation

Inventor： Suyoung Bang ,  Minki Cho ,  Pascal Meinerzhagen ,  Muhammad Khellah

IPC: H03K17/16 ,  H03K17/10 ,  H03K17/284

Abstract: An apparatus is provided which comprises: a first power supply rail to provide a first power supply voltage; a second power supply rail to provide a second power supply voltage, wherein the first power supply voltage is higher than the second power supply voltage; a first circuitry coupled to the first and second supply rails, wherein the first circuitry is to operate using the first supply voltage, and wherein the first circuitry is to inject charge on to the second power supply rail in response to a droop indication; and a second circuitry to detect voltage droop on the second power supply rail, wherein the second circuitry is to generate the droop indication for the first circuitry.

公开(公告)号：US09685208B2

公开(公告)日：2017-06-20

申请号：US15094755

申请日：2016-04-08

Applicant: Intel Corporation

Inventor： Jaydeep P. Kulkarni ,  Anupama Thaploo ,  Iqbal Rajwani ,  Kyung-Hoae Koo ,  Eric A. Karl ,  Muhammad Khellah

IPC: G11C7/00 ,  G11C7/12 ,  G11C7/22 ,  G11C17/16 ,  G11C7/10 ,  G11C11/419

CPC classification number: G11C7/12 ,  G11C7/1048 ,  G11C7/1069 ,  G11C7/22 ,  G11C11/419 ,  G11C17/16 ,  G11C2207/005

Abstract: Embodiments include apparatuses, methods, and systems related to an assist circuit that may be coupled to one or more components of a memory system to selectively lower a supply voltage that is delivered to the component. For example, the assist circuit may be coupled to a plurality of bitcells (e.g., register file bitcells). The assist circuit may selectively lower the supply voltage delivered to the bitcells during at least a portion of a write operation and/or during an inactive state of the bitcells. Additionally, or alternatively, the assist circuit may be coupled to a read circuit to selectively lower the supply voltage delivered to the read circuit during an inactive state of the read circuit. The assist circuit may include a control transistor coupled in parallel with one or more diodes between a main supply rail and a supply node of the bitcells and/or read circuit.

公开(公告)号：US11774919B2

公开(公告)日：2023-10-03

申请号：US17125768

申请日：2020-12-17

Applicant: Intel Corporation

Inventor： Suyoung Bang ,  Wootaek Lim ,  Eric Samson ,  Charles Augustine ,  Muhammad Khellah

IPC: G05B11/42 ,  G05B11/12 ,  G05F1/46

CPC classification number: G05B11/12 ,  G05F1/46

Abstract: A distributed and scalable all-digital LDO (D-DLDO) voltage regulator allowing rapid scaling across technology nodes. The distributed DLDO includes many tillable DLDO units regulating a single supply voltage with a shared power distribution network (PDN). The D-DLDO includes an all-digital proportional-integral-derivative (PID) controller that receives a first code indicative of a voltage behavior on a power supply rail. A droop detector is provided to compare the first code with a threshold to determine a droop event, wherein information about the droop event is provided to the PID controller, wherein the PID controller generates a second code according to the first code and the information about the droop event. The DLDO includes a plurality of power gates that receive the second code.

公开(公告)号：US20210242872A1

公开(公告)日：2021-08-05

申请号：US17020667

申请日：2020-09-14

Applicant: Intel Corporation

Inventor： Suyoung Bang ,  Eric Samson ,  Wootaek Lim ,  Charles Augustine ,  Muhammad Khellah

IPC: H03L7/081 ,  G04F10/00 ,  H03L7/085

Abstract: An all-digital voltage monitor (ADVM) generates a multi-bit output code that changes in proportion to a voltage being monitored, by leveraging the voltage impact on a gate delay. ADVM utilizes a simple delay chain, which receives a clock-cycle-long pulse every clock cycle, such that the monitored supply voltage is sampled for one full cycle every cycle. The outputs of all delay cells of the delay chain collectively represents a current voltage state as a digital thermometer code. In AVDM, a voltage droop event thus results in a decrease in the output code from a nominal value, while an overshoot results in an increase in the output code.

公开(公告)号：US10784865B1

公开(公告)日：2020-09-22

申请号：US16413110

申请日：2019-05-15

Applicant: Intel Corporation

Inventor： Pascal Meinerzhagen ,  Vivek De ,  Muhammad Khellah

IPC: H03K19/003 ,  H03K5/14 ,  G06F1/10 ,  H03K5/135

Abstract: A minimum delay error apparatus such as a minimum delay error detection, prediction, correction, repair, prevention, and/or avoidance apparatus includes a minimum delay path replica circuit. The minimum delay path replica circuit can detect or predict, and subsequently can correct or avoid, minimum delay errors in data paths of digital circuits using pulsed latches.

公开(公告)号：US10483961B2

公开(公告)日：2019-11-19

申请号：US15925396

申请日：2018-03-19

Applicant: Intel Corporation

Inventor： Suyoung Bang ,  Minki Cho ,  Pascal Meinerzhagen ,  Muhammad Khellah

IPC: H03L5/00 ,  H03K17/16 ,  H03K17/284 ,  H03K17/10

Abstract: An apparatus is provided which comprises: a first power supply rail to provide a first power supply voltage; a second power supply rail to provide a second power supply voltage, wherein the first power supply voltage is higher than the second power supply voltage; a first circuitry coupled to the first and second supply rails, wherein the first circuitry is to operate using the first supply voltage, and wherein the first circuitry is to inject charge on to the second power supply rail in response to a droop indication; and a second circuitry to detect voltage droop on the second power supply rail, wherein the second circuitry is to generate the droop indication for the first circuitry.

公开(公告)号：US20220091652A1

公开(公告)日：2022-03-24

申请号：US17128076

申请日：2020-12-19

Applicant: Intel Corporation

Inventor： Charles Augustine ,  Pascal Meinerzhagen ,  Suyoung Bang ,  Abdullah Afzal ,  Karthik Subramanian ,  Muhammad Khellah ,  Arvind Raman

IPC: G06F1/324 ,  H03K19/0175 ,  G06F1/12 ,  G06F1/08 ,  G06F1/3296

Abstract: Described is a controller that provides in-situ state retention using a closed loop global retention clamp. The controller addresses di/dt and reliability constraints using an adaptive scheme where steps with smaller current are quickly changed whereas steps with larger current are changed slowly. The loop controller of a voltage regulator is modified for controlling not only retention Vmin during a low power state (e.g., C1LP), but also to control fast wake up the low power state (e.g., from C1LP and from C6).

公开(公告)号：US20210319022A1

公开(公告)日：2021-10-14

申请号：US17358495

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Srajudheen Makkadayil ,  Somnath Paul ,  Shabbir Saifee ,  Bakshree Mishra ,  Vidhya Thyagarajan ,  Manoj Velayudha ,  Muhammad Khellah ,  Aniekeme Udofia

IPC: G06F16/2453 ,  G06F16/22

Abstract: Systems, apparatuses and methods include technology that determines, with a first processing engine of a plurality of processing engines, a first partial similarity measurement based on a first portion of a query vector and a first portion of a first candidate vector. The technology determines, with a second processing engine of the plurality of processing engines, a total similarity measurement based on the query vector and a second candidate vector. The technology determines, with the first processing engine, whether to compare a second portion of the query vector to a second portion of the first candidate vector based on the first partial similarity measurement and the total similarity measurement.

公开(公告)号：US10908673B2

公开(公告)日：2021-02-02

申请号：US15891081

申请日：2018-02-07

Applicant: Intel Corporation

Inventor： Pascal Meinerzhagen ,  Stephen Kim ,  Dongmin Yoon ,  Minki Cho ,  Muhammad Khellah

IPC: G06F1/32 ,  G05F1/563 ,  G05F1/59 ,  G06F1/3296 ,  G06F1/3287 ,  G06F1/3234 ,  G06F1/324

Abstract: An apparatus is provided which comprises: a first device coupled to a first power supply rail; a second device coupled in series with the first device, wherein the second device is coupled to a second power supply rail; and a third device coupled to the first and second power supply rails, wherein the first device is controllable by a first input, wherein the second device is controllable by a second input, wherein the third device is controllable by a third input, and wherein the first input is an analog bias between a high power supply level and a ground supply level.